@@ -4366,18 +4366,18 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
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static int pci_quirk_cavium_acs (struct pci_dev * dev , u16 acs_flags )
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{
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+ if (!pci_quirk_cavium_acs_match (dev ))
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+ return - ENOTTY ;
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+
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/*
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- * Cavium root ports don't advertise an ACS capability. However,
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+ * Cavium Root Ports don't advertise an ACS capability. However,
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* the RTL internally implements similar protection as if ACS had
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- * Request Redirection, Completion Redirection, Source Validation ,
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+ * Source Validation, Request Redirection, Completion Redirection ,
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* and Upstream Forwarding features enabled. Assert that the
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* hardware implements and enables equivalent ACS functionality for
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* these flags.
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*/
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- acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF );
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-
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- if (!pci_quirk_cavium_acs_match (dev ))
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- return - ENOTTY ;
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+ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF );
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return acs_flags ? 0 : 1 ;
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}
@@ -4395,7 +4395,7 @@ static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
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}
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/*
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- * Many Intel PCH root ports do provide ACS-like features to disable peer
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+ * Many Intel PCH Root Ports do provide ACS-like features to disable peer
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* transactions and validate bus numbers in requests, but do not provide an
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* actual PCIe ACS capability. This is the list of device IDs known to fall
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* into that category as provided by Intel in Red Hat bugzilla 1037684.
@@ -4443,37 +4443,34 @@ static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
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return false;
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}
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- #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV )
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+ #define INTEL_PCH_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF )
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static int pci_quirk_intel_pch_acs (struct pci_dev * dev , u16 acs_flags )
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{
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- u16 flags = dev -> dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
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- INTEL_PCH_ACS_FLAGS : 0 ;
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-
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if (!pci_quirk_intel_pch_acs_match (dev ))
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return - ENOTTY ;
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- return acs_flags & ~flags ? 0 : 1 ;
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+ if (dev -> dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK )
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+ acs_flags &= ~(INTEL_PCH_ACS_FLAGS );
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+
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+ return acs_flags ? 0 : 1 ;
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}
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/*
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- * These QCOM root ports do provide ACS-like features to disable peer
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+ * These QCOM Root Ports do provide ACS-like features to disable peer
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* transactions and validate bus numbers in requests, but do not provide an
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* actual PCIe ACS capability. Hardware supports source validation but it
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* will report the issue as Completer Abort instead of ACS Violation.
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- * Hardware doesn't support peer-to-peer and each root port is a root
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- * complex with unique segment numbers. It is not possible for one root
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- * port to pass traffic to another root port . All PCIe transactions are
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- * terminated inside the root port .
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+ * Hardware doesn't support peer-to-peer and each Root Port is a Root
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+ * Complex with unique segment numbers. It is not possible for one Root
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+ * Port to pass traffic to another Root Port . All PCIe transactions are
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+ * terminated inside the Root Port .
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*/
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static int pci_quirk_qcom_rp_acs (struct pci_dev * dev , u16 acs_flags )
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{
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- u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV );
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- int ret = acs_flags & ~flags ? 0 : 1 ;
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-
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- pci_info (dev , "Using QCOM ACS Quirk (%d)\n" , ret );
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+ acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF );
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- return ret ;
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+ return acs_flags ? 0 : 1 ;
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}
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static int pci_quirk_al_acs (struct pci_dev * dev , u16 acs_flags )
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