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net: wan: framer: Add support for the Lantiq PEF2256 framer
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by: Herve Codina <[email protected]> Reviewed-by: Christophe Leroy <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Acked-by: Jakub Kicinski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/net/wan/framer/Kconfig

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@@ -22,4 +22,21 @@ if FRAMER
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config GENERIC_FRAMER
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bool
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config FRAMER_PEF2256
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tristate "Lantiq PEF2256"
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depends on OF
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depends on HAS_IOMEM
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select GENERIC_FRAMER
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select MFD_CORE
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select REGMAP_MMIO
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help
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Enable support for the Lantiq PEF2256 (FALC56) framer.
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The PEF2256 is a framer and line interface between analog E1/T1/J1
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line and a digital PCM bus.
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If unsure, say N.
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To compile this driver as a module, choose M here: the
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module will be called framer-pef2256.
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endif # FRAMER

‎drivers/net/wan/framer/Makefile

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#
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obj-$(CONFIG_GENERIC_FRAMER) += framer-core.o
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obj-$(CONFIG_FRAMER_PEF2256) += pef2256/

‎drivers/net/wan/framer/pef2256/Makefile

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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the pef2256 driver.
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#
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obj-$(CONFIG_FRAMER_PEF2256) += framer-pef2256.o
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framer-pef2256-objs := pef2256.o

‎drivers/net/wan/framer/pef2256/pef2256-regs.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PEF2256 registers definition
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*
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* Copyright 2023 CS GROUP France
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*
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* Author: Herve Codina <[email protected]>
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*/
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#ifndef __PEF2256_REGS_H__
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#define __PEF2256_REGS_H__
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#include "linux/bitfield.h"
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/* Command Register */
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#define PEF2256_CMDR 0x02
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#define PEF2256_CMDR_RRES BIT(6)
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#define PEF2256_CMDR_XRES BIT(4)
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#define PEF2256_CMDR_SRES BIT(0)
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/* Interrupt Mask Register 0..5 */
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#define PEF2256_IMR0 0x14
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#define PEF2256_IMR1 0x15
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#define PEF2256_IMR2 0x16
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#define PEF2256_IMR3 0x17
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#define PEF2256_IMR4 0x18
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#define PEF2256_IMR5 0x19
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/* Framer Mode Register 0 */
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#define PEF2256_FMR0 0x1C
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#define PEF2256_FMR0_XC_MASK GENMASK(7, 6)
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#define PEF2256_FMR0_XC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
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#define PEF2256_FMR0_XC_CMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
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#define PEF2256_FMR0_XC_AMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
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#define PEF2256_FMR0_XC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
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#define PEF2256_FMR0_RC_MASK GENMASK(5, 4)
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#define PEF2256_FMR0_RC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
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#define PEF2256_FMR0_RC_CMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
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#define PEF2256_FMR0_RC_AMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
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#define PEF2256_FMR0_RC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
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/* Framer Mode Register 1 */
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#define PEF2256_FMR1 0x1D
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#define PEF2256_FMR1_XFS BIT(3)
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#define PEF2256_FMR1_ECM BIT(2)
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/* SSD is defined on 2 bits. The other bit is on SIC1 register */
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#define PEF2256_FMR1_SSD_MASK GENMASK(1, 1)
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#define PEF2256_FMR1_SSD_2048 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
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#define PEF2256_FMR1_SSD_4096 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
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#define PEF2256_FMR1_SSD_8192 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
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#define PEF2256_FMR1_SSD_16384 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
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/* Framer Mode Register 2 */
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#define PEF2256_FMR2 0x1E
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#define PEF2256_FMR2_RFS_MASK GENMASK(7, 6)
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#define PEF2256_FMR2_RFS_DOUBLEFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0)
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#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2)
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#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)
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#define PEF2256_FMR2_AXRA BIT(1)
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/* Transmit Service Word */
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#define PEF2256_XSW 0x20
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#define PEF2256_XSW_XSIS BIT(7)
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#define PEF2256_XSW_XTM BIT(6)
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#define PEF2256_XSW_XY_MASK GENMASK(5, 0)
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#define PEF2256_XSW_XY(_v) FIELD_PREP(PEF2256_XSW_XY_MASK, _v)
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/* Transmit Spare Bits */
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#define PEF2256_XSP 0x21
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#define PEF2256_XSP_XSIF BIT(2)
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/* Transmit Control 0..1 */
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#define PEF2256_XC0 0x22
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#define PEF2256_XC1 0x23
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/* Receive Control 0 */
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#define PEF2256_RC0 0x24
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#define PEF2256_RC0_SWD BIT(7)
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#define PEF2256_RC0_ASY4 BIT(6)
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/* Receive Control 1 */
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#define PEF2256_RC1 0x25
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/* Transmit Pulse Mask 0..1 */
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#define PEF2256_XPM0 0x26
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#define PEF2256_XPM1 0x27
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/* Transmit Pulse Mask 2 */
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#define PEF2256_XPM2 0x28
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#define PEF2256_XPM2_XLT BIT(6)
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/* Transparent Service Word Mask */
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#define PEF2256_TSWM 0x29
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/* Line Interface Mode 0 */
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#define PEF2256_LIM0 0x36
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#define PEF2256_2X_LIM0_BIT3 BIT(3) /* v2.x, described as a forced '1' bit */
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#define PEF2256_LIM0_MAS BIT(0)
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/* Line Interface Mode 1 */
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#define PEF2256_LIM1 0x37
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#define PEF2256_12_LIM1_RIL_MASK GENMASK(6, 4)
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#define PEF2256_12_LIM1_RIL_910 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x0)
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#define PEF2256_12_LIM1_RIL_740 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x1)
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#define PEF2256_12_LIM1_RIL_590 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x2)
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#define PEF2256_12_LIM1_RIL_420 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3)
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#define PEF2256_12_LIM1_RIL_320 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x4)
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#define PEF2256_12_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x5)
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#define PEF2256_12_LIM1_RIL_160 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x6)
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#define PEF2256_12_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x7)
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#define PEF2256_2X_LIM1_RIL_MASK GENMASK(6, 4)
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#define PEF2256_2X_LIM1_RIL_2250 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x0)
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#define PEF2256_2X_LIM1_RIL_1100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x1)
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#define PEF2256_2X_LIM1_RIL_600 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x2)
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#define PEF2256_2X_LIM1_RIL_350 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3)
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#define PEF2256_2X_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x4)
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#define PEF2256_2X_LIM1_RIL_140 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x5)
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#define PEF2256_2X_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x6)
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#define PEF2256_2X_LIM1_RIL_50 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x7)
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/* Pulse Count Detection */
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#define PEF2256_PCD 0x38
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/* Pulse Count Recovery */
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#define PEF2256_PCR 0x39
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/* Line Interface Mode 2 */
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#define PEF2256_LIM2 0x3A
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#define PEF2256_LIM2_SLT_MASK GENMASK(5, 4)
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#define PEF2256_LIM2_SLT_THR55 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x0)
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#define PEF2256_LIM2_SLT_THR67 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x1)
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#define PEF2256_LIM2_SLT_THR50 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x2)
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#define PEF2256_LIM2_SLT_THR45 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3)
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#define PEF2256_LIM2_ELT BIT(2)
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/* System Interface Control 1 */
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#define PEF2256_SIC1 0x3E
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#define PEF2256_SIC1_SSC_MASK (BIT(7) | BIT(3))
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#define PEF2256_SIC1_SSC_2048 (0)
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#define PEF2256_SIC1_SSC_4096 BIT(3)
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#define PEF2256_SIC1_SSC_8192 BIT(7)
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#define PEF2256_SIC1_SSC_16384 (BIT(7) | BIT(3))
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/* SSD is defined on 2 bits. The other bit is on FMR1 register */
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#define PEF2256_SIC1_SSD_MASK GENMASK(6, 6)
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#define PEF2256_SIC1_SSD_2048 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
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#define PEF2256_SIC1_SSD_4096 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
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#define PEF2256_SIC1_SSD_8192 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
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#define PEF2256_SIC1_SSD_16384 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
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#define PEF2256_SIC1_RBS_MASK GENMASK(5, 4)
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#define PEF2256_SIC1_RBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x0)
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#define PEF2256_SIC1_RBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x1)
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#define PEF2256_SIC1_RBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x2)
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#define PEF2256_SIC1_RBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3)
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#define PEF2256_SIC1_XBS_MASK GENMASK(1, 0)
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#define PEF2256_SIC1_XBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x0)
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#define PEF2256_SIC1_XBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x1)
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#define PEF2256_SIC1_XBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x2)
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#define PEF2256_SIC1_XBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3)
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/* System Interface Control 2 */
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#define PEF2256_SIC2 0x3F
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#define PEF2256_SIC2_SICS_MASK GENMASK(3, 1)
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#define PEF2256_SIC2_SICS(_v) FIELD_PREP(PEF2256_SIC2_SICS_MASK, _v)
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/* System Interface Control 3 */
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#define PEF2256_SIC3 0x40
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#define PEF2256_SIC3_RTRI BIT(5)
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#define PEF2256_SIC3_RESX BIT(3)
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#define PEF2256_SIC3_RESR BIT(2)
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/* Clock Mode Register 1 */
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#define PEF2256_CMR1 0x44
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#define PEF2256_CMR1_RS_MASK GENMASK(5, 4)
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#define PEF2256_CMR1_RS_DPLL FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x0)
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#define PEF2256_CMR1_RS_DPLL_LOS_HIGH FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x1)
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#define PEF2256_CMR1_RS_DCOR_2048 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x2)
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#define PEF2256_CMR1_RS_DCOR_8192 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3)
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#define PEF2256_CMR1_DCS BIT(3)
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/* Clock Mode Register 2 */
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#define PEF2256_CMR2 0x45
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#define PEF2256_CMR2_DCOXC BIT(5)
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/* Global Configuration Register */
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#define PEF2256_GCR 0x46
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#define PEF2256_GCR_SCI BIT(6)
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#define PEF2256_GCR_ECMC BIT(4)
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/* Port Configuration 5 */
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#define PEF2256_PC5 0x84
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#define PEF2256_PC5_CRP BIT(0)
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/* Global Port Configuration 1 */
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#define PEF2256_GPC1 0x85
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#define PEF2256_GPC1_CSFP_MASK GENMASK(7, 5)
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#define PEF2256_GPC1_CSFP_SEC_IN_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x0)
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#define PEF2256_GPC1_CSFP_SEC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x1)
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#define PEF2256_GPC1_CSFP_FSC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x2)
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#define PEF2256_GPC1_CSFP_FSC_OUT_LOW FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3)
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/* Port Configuration 6 */
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#define PEF2256_PC6 0x86
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/* Global Counter Mode n=1..8 */
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#define PEF2256_GCM(_n) (0x92 + (_n) - 1)
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#define PEF2256_GCM1 0x92
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#define PEF2256_GCM2 0x93
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#define PEF2256_GCM3 0x94
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#define PEF2256_GCM4 0x95
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#define PEF2256_GCM5 0x96
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#define PEF2256_GCM6 0x97
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#define PEF2256_GCM7 0x98
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#define PEF2256_GCM8 0x99
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/* Version Status Register */
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#define PEF2256_VSTR 0x4A
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#define PEF2256_VSTR_VERSION_12 0x00
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#define PEF2256_VSTR_VERSION_21 0x10
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#define PEF2256_VSTR_VERSION_2x 0x05
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/* Framer Receive Status 0 */
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#define PEF2256_FRS0 0x4C
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#define PEF2256_FRS0_LOS BIT(7)
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#define PEF2256_FRS0_AIS BIT(6)
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/* Interrupt Status Register 0..5 */
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#define PEF2256_ISR(_n) (0x68 + (_n))
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#define PEF2256_ISR0 0x68
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#define PEF2256_ISR1 0x69
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#define PEF2256_ISR2 0x6A
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#define PEF2256_ISR3 0x6B
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#define PEF2256_ISR4 0x6C
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#define PEF2256_ISR5 0x6D
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/* Global Interrupt Status */
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#define PEF2256_GIS 0x6E
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#define PEF2256_GIS_ISR(_n) BIT(_n)
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/* Wafer Identification Register */
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#define PEF2256_WID 0xEC
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#define PEF2256_12_WID_MASK GENMASK(1, 0)
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#define PEF2256_12_WID_VERSION_12 FIELD_PREP_CONST(PEF2256_12_WID_MASK, 0x3)
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#define PEF2256_2X_WID_MASK GENMASK(7, 6)
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#define PEF2256_2X_WID_VERSION_21 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x0)
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#define PEF2256_2X_WID_VERSION_22 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x1)
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/* IMR2/ISR2 Interrupts common bits */
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#define PEF2256_INT2_AIS BIT(3)
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#define PEF2256_INT2_LOS BIT(2)
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#endif /* __PEF2256_REGS_H__ */

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