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Sowjanya Komatinenithierryreding
Sowjanya Komatineni
authored and
thierryreding
committed
clk: tegra: Remove CLK_M_DIV fixed clocks
Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of PMC clocks for Tegra30 through Tegra210. Tegra PMC clock parents are changed to use OSC_DIV clocks. So, this patch removes CLK_M_DIV fixed clocks Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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-45
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6 files changed

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‎drivers/clk/tegra/clk-id.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,6 @@ enum clk_id {
4444
tegra_clk_clk72Mhz,
4545
tegra_clk_clk72Mhz_8,
4646
tegra_clk_clk_m,
47-
tegra_clk_clk_m_div2,
48-
tegra_clk_clk_m_div4,
4947
tegra_clk_osc,
5048
tegra_clk_osc_div2,
5149
tegra_clk_osc_div4,

‎drivers/clk/tegra/clk-tegra-fixed.c

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -105,22 +105,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
105105
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
106106
*dt_clk = clk;
107107
}
108-
109-
/* clk_m_div2 */
110-
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
111-
if (dt_clk) {
112-
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
113-
CLK_SET_RATE_PARENT, 1, 2);
114-
*dt_clk = clk;
115-
}
116-
117-
/* clk_m_div4 */
118-
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
119-
if (dt_clk) {
120-
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
121-
CLK_SET_RATE_PARENT, 1, 4);
122-
*dt_clk = clk;
123-
}
124108
}
125109

126110
void tegra_clk_osc_resume(void __iomem *clk_base)

‎drivers/clk/tegra/clk-tegra114.c

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -735,8 +735,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
735735
[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
736736
[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
737737
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
738-
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
739-
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
740738
[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
741739
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
742740
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
@@ -818,8 +816,6 @@ static struct tegra_devclk devclks[] __initdata = {
818816
{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
819817
{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
820818
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
821-
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
822-
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
823819
{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
824820
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
825821
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
@@ -906,17 +902,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
906902
/* clk_32k */
907903
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
908904
clks[TEGRA114_CLK_CLK_32K] = clk;
909-
910-
/* clk_m_div2 */
911-
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
912-
CLK_SET_RATE_PARENT, 1, 2);
913-
clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
914-
915-
/* clk_m_div4 */
916-
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
917-
CLK_SET_RATE_PARENT, 1, 4);
918-
clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
919-
920905
}
921906

922907
static void __init tegra114_pll_init(void __iomem *clk_base,

‎drivers/clk/tegra/clk-tegra124.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -860,8 +860,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
860860
[tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
861861
[tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
862862
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863-
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
864-
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
865863
[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
866864
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
867865
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
@@ -944,8 +942,6 @@ static struct tegra_devclk devclks[] __initdata = {
944942
{ .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
945943
{ .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
946944
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
947-
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
948-
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
949945
{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
950946
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
951947
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },

‎drivers/clk/tegra/clk-tegra210.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2371,8 +2371,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
23712371
[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
23722372
[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
23732373
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2374-
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2375-
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
23762374
[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
23772375
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
23782376
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
@@ -2500,8 +2498,6 @@ static struct tegra_devclk devclks[] __initdata = {
25002498
{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
25012499
{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
25022500
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2503-
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2504-
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
25052501
{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
25062502
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
25072503
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },

‎drivers/clk/tegra/clk-tegra30.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -581,8 +581,6 @@ static struct tegra_devclk devclks[] __initdata = {
581581
{ .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
582582
{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
583583
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
584-
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
585-
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
586584
{ .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
587585
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
588586
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
@@ -686,8 +684,6 @@ static struct tegra_devclk devclks[] __initdata = {
686684
static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
687685
[tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
688686
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
689-
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
690-
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
691687
[tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
692688
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
693689
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },

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