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clk: qcom: gcc-x1e80100: Don't use parking clk_ops for QUPs
Per Stephen Boyd's explanation in the link below, QUP RCG clocks do not need to be parked when switching frequency. A side-effect in parking to a lower frequency can be a momentary invalid clock driven on an in-use serial peripheral. This can cause "junk" to spewed out of a UART as a low-impact example. On the x1e80100-crd this serial port junk can be observed on linux-next. Apply a similar fix to the x1e80100 Global Clock controller to remediate. Link: https://lore.kernel.org/all/[email protected]/ Fixes: 161b7c4 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Fixes: 929c75d ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") Suggested-by: Neil Armstrong <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/qcom/gcc-x1e80100.c‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
670670
.parent_data = gcc_parent_data_0,
671671
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
672672
.flags = CLK_SET_RATE_PARENT,
673-
.ops = &clk_rcg2_shared_ops,
673+
.ops = &clk_rcg2_ops,
674674
};
675675

676676
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -687,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
687687
.parent_data = gcc_parent_data_0,
688688
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
689689
.flags = CLK_SET_RATE_PARENT,
690-
.ops = &clk_rcg2_shared_ops,
690+
.ops = &clk_rcg2_ops,
691691
};
692692

693693
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -719,7 +719,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
719719
.parent_data = gcc_parent_data_0,
720720
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
721721
.flags = CLK_SET_RATE_PARENT,
722-
.ops = &clk_rcg2_shared_ops,
722+
.ops = &clk_rcg2_ops,
723723
};
724724

725725
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -736,7 +736,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
736736
.parent_data = gcc_parent_data_0,
737737
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
738738
.flags = CLK_SET_RATE_PARENT,
739-
.ops = &clk_rcg2_shared_ops,
739+
.ops = &clk_rcg2_ops,
740740
};
741741

742742
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -768,7 +768,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
768768
.parent_data = gcc_parent_data_0,
769769
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
770770
.flags = CLK_SET_RATE_PARENT,
771-
.ops = &clk_rcg2_shared_ops,
771+
.ops = &clk_rcg2_ops,
772772
};
773773

774774
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -785,7 +785,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
785785
.parent_data = gcc_parent_data_0,
786786
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
787787
.flags = CLK_SET_RATE_PARENT,
788-
.ops = &clk_rcg2_shared_ops,
788+
.ops = &clk_rcg2_ops,
789789
};
790790

791791
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -802,7 +802,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
802802
.parent_data = gcc_parent_data_0,
803803
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
804804
.flags = CLK_SET_RATE_PARENT,
805-
.ops = &clk_rcg2_shared_ops,
805+
.ops = &clk_rcg2_ops,
806806
};
807807

808808
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
819819
.parent_data = gcc_parent_data_0,
820820
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
821821
.flags = CLK_SET_RATE_PARENT,
822-
.ops = &clk_rcg2_shared_ops,
822+
.ops = &clk_rcg2_ops,
823823
};
824824

825825
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -836,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
836836
.parent_data = gcc_parent_data_0,
837837
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
838838
.flags = CLK_SET_RATE_PARENT,
839-
.ops = &clk_rcg2_shared_ops,
839+
.ops = &clk_rcg2_ops,
840840
};
841841

842842
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -853,7 +853,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
853853
.parent_data = gcc_parent_data_0,
854854
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
855855
.flags = CLK_SET_RATE_PARENT,
856-
.ops = &clk_rcg2_shared_ops,
856+
.ops = &clk_rcg2_ops,
857857
};
858858

859859
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -870,7 +870,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
870870
.parent_data = gcc_parent_data_0,
871871
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
872872
.flags = CLK_SET_RATE_PARENT,
873-
.ops = &clk_rcg2_shared_ops,
873+
.ops = &clk_rcg2_ops,
874874
};
875875

876876
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -887,7 +887,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
887887
.parent_data = gcc_parent_data_0,
888888
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
889889
.flags = CLK_SET_RATE_PARENT,
890-
.ops = &clk_rcg2_shared_ops,
890+
.ops = &clk_rcg2_ops,
891891
};
892892

893893
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -904,7 +904,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
904904
.parent_data = gcc_parent_data_0,
905905
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
906906
.flags = CLK_SET_RATE_PARENT,
907-
.ops = &clk_rcg2_shared_ops,
907+
.ops = &clk_rcg2_ops,
908908
};
909909

910910
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -921,7 +921,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
921921
.parent_data = gcc_parent_data_0,
922922
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
923923
.flags = CLK_SET_RATE_PARENT,
924-
.ops = &clk_rcg2_shared_ops,
924+
.ops = &clk_rcg2_ops,
925925
};
926926

927927
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -938,7 +938,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
938938
.parent_data = gcc_parent_data_0,
939939
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
940940
.flags = CLK_SET_RATE_PARENT,
941-
.ops = &clk_rcg2_shared_ops,
941+
.ops = &clk_rcg2_ops,
942942
};
943943

944944
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -955,7 +955,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
955955
.parent_data = gcc_parent_data_0,
956956
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
957957
.flags = CLK_SET_RATE_PARENT,
958-
.ops = &clk_rcg2_shared_ops,
958+
.ops = &clk_rcg2_ops,
959959
};
960960

961961
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -972,7 +972,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
972972
.parent_data = gcc_parent_data_0,
973973
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
974974
.flags = CLK_SET_RATE_PARENT,
975-
.ops = &clk_rcg2_shared_ops,
975+
.ops = &clk_rcg2_ops,
976976
};
977977

978978
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -989,7 +989,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
989989
.parent_data = gcc_parent_data_0,
990990
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
991991
.flags = CLK_SET_RATE_PARENT,
992-
.ops = &clk_rcg2_shared_ops,
992+
.ops = &clk_rcg2_ops,
993993
};
994994

995995
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -1006,7 +1006,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
10061006
.parent_data = gcc_parent_data_0,
10071007
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
10081008
.flags = CLK_SET_RATE_PARENT,
1009-
.ops = &clk_rcg2_shared_ops,
1009+
.ops = &clk_rcg2_ops,
10101010
};
10111011

10121012
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -1023,7 +1023,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
10231023
.parent_data = gcc_parent_data_0,
10241024
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
10251025
.flags = CLK_SET_RATE_PARENT,
1026-
.ops = &clk_rcg2_shared_ops,
1026+
.ops = &clk_rcg2_ops,
10271027
};
10281028

10291029
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -1040,7 +1040,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
10401040
.parent_data = gcc_parent_data_0,
10411041
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
10421042
.flags = CLK_SET_RATE_PARENT,
1043-
.ops = &clk_rcg2_shared_ops,
1043+
.ops = &clk_rcg2_ops,
10441044
};
10451045

10461046
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -1057,7 +1057,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
10571057
.parent_data = gcc_parent_data_0,
10581058
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
10591059
.flags = CLK_SET_RATE_PARENT,
1060-
.ops = &clk_rcg2_shared_ops,
1060+
.ops = &clk_rcg2_ops,
10611061
};
10621062

10631063
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -1074,7 +1074,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
10741074
.parent_data = gcc_parent_data_8,
10751075
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
10761076
.flags = CLK_SET_RATE_PARENT,
1077-
.ops = &clk_rcg2_shared_ops,
1077+
.ops = &clk_rcg2_ops,
10781078
};
10791079

10801080
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@@ -1091,7 +1091,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
10911091
.parent_data = gcc_parent_data_0,
10921092
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
10931093
.flags = CLK_SET_RATE_PARENT,
1094-
.ops = &clk_rcg2_shared_ops,
1094+
.ops = &clk_rcg2_ops,
10951095
};
10961096

10971097
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {

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