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drivers/gpu/drm/i915/gt/uc Expand file tree Collapse file tree 3 files changed +8
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lines changed Original file line number Diff line number Diff line change @@ -319,6 +319,12 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
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if (!RCS_MASK (gt ))
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flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST ;
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+ /* Wa_14018913170 */
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+ if (GUC_FIRMWARE_VER (guc ) >= MAKE_GUC_VER (70 , 7 , 0 )) {
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+ if (IS_DG2 (gt -> i915 ) || IS_METEORLAKE (gt -> i915 ) || IS_PONTEVECCHIO (gt -> i915 ))
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+ flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6 ;
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+ }
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+
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return flags ;
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}
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Original file line number Diff line number Diff line change @@ -295,6 +295,7 @@ struct intel_guc {
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#define MAKE_GUC_VER (maj , min , pat ) (((maj) << 16) | ((min) << 8) | (pat))
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#define MAKE_GUC_VER_STRUCT (ver ) MAKE_GUC_VER((ver).major, (ver).minor, (ver).patch)
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#define GUC_SUBMIT_VER (guc ) MAKE_GUC_VER_STRUCT((guc)->submission_version)
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+ #define GUC_FIRMWARE_VER (guc ) MAKE_GUC_VER_STRUCT((guc)->fw.file_selected.ver)
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static inline struct intel_guc * log_to_guc (struct intel_guc_log * log )
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{
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#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
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#define GUC_WA_POLLCS BIT(18)
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#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
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+ #define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
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#define GUC_CTL_FEATURE 2
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#define GUC_CTL_ENABLE_SLPC BIT(2)
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