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airliedairlied
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Merge tag 'drm-etnaviv-fixes-2024-04-25' of https://git.pengutronix.de/git/lst/linux into drm-fixes
- fix GC7000 TX clock gating - revert NPU UAPI changes Signed-off-by: Dave Airlie <[email protected]> From: Lucas Stach <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 86ab998 + e877d70 commit ca382d6

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4 files changed

+2
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‎drivers/gpu/drm/etnaviv/etnaviv_gpu.c

Lines changed: 2 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -164,26 +164,6 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
164164
*value = gpu->identity.eco_id;
165165
break;
166166

167-
case ETNAVIV_PARAM_GPU_NN_CORE_COUNT:
168-
*value = gpu->identity.nn_core_count;
169-
break;
170-
171-
case ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE:
172-
*value = gpu->identity.nn_mad_per_core;
173-
break;
174-
175-
case ETNAVIV_PARAM_GPU_TP_CORE_COUNT:
176-
*value = gpu->identity.tp_core_count;
177-
break;
178-
179-
case ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE:
180-
*value = gpu->identity.on_chip_sram_size;
181-
break;
182-
183-
case ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE:
184-
*value = gpu->identity.axi_sram_size;
185-
break;
186-
187167
default:
188168
DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
189169
return -EINVAL;
@@ -663,8 +643,8 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
663643
/* Disable TX clock gating on affected core revisions. */
664644
if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
665645
etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
666-
etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
667-
etnaviv_is_model_rev(gpu, GC2000, 0x6203))
646+
etnaviv_is_model_rev(gpu, GC7000, 0x6202) ||
647+
etnaviv_is_model_rev(gpu, GC7000, 0x6203))
668648
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
669649

670650
/* Disable SE and RA clock gating on affected core revisions. */

‎drivers/gpu/drm/etnaviv/etnaviv_gpu.h

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -54,18 +54,6 @@ struct etnaviv_chip_identity {
5454
/* Number of Neural Network cores. */
5555
u32 nn_core_count;
5656

57-
/* Number of MAD units per Neural Network core. */
58-
u32 nn_mad_per_core;
59-
60-
/* Number of Tensor Processing cores. */
61-
u32 tp_core_count;
62-
63-
/* Size in bytes of the SRAM inside the NPU. */
64-
u32 on_chip_sram_size;
65-
66-
/* Size in bytes of the SRAM across the AXI bus. */
67-
u32 axi_sram_size;
68-
6957
/* Size of the vertex cache. */
7058
u32 vertex_cache_size;
7159

‎drivers/gpu/drm/etnaviv/etnaviv_hwdb.c

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
1717
.thread_count = 128,
1818
.shader_core_count = 1,
1919
.nn_core_count = 0,
20-
.nn_mad_per_core = 0,
21-
.tp_core_count = 0,
22-
.on_chip_sram_size = 0,
23-
.axi_sram_size = 0,
2420
.vertex_cache_size = 8,
2521
.vertex_output_buffer_size = 1024,
2622
.pixel_pipes = 1,
@@ -52,11 +48,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
5248
.register_max = 64,
5349
.thread_count = 256,
5450
.shader_core_count = 1,
55-
.nn_core_count = 0,
56-
.nn_mad_per_core = 0,
57-
.tp_core_count = 0,
58-
.on_chip_sram_size = 0,
59-
.axi_sram_size = 0,
6051
.vertex_cache_size = 8,
6152
.vertex_output_buffer_size = 512,
6253
.pixel_pipes = 1,
@@ -89,10 +80,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
8980
.thread_count = 512,
9081
.shader_core_count = 2,
9182
.nn_core_count = 0,
92-
.nn_mad_per_core = 0,
93-
.tp_core_count = 0,
94-
.on_chip_sram_size = 0,
95-
.axi_sram_size = 0,
9683
.vertex_cache_size = 16,
9784
.vertex_output_buffer_size = 1024,
9885
.pixel_pipes = 1,
@@ -125,10 +112,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
125112
.thread_count = 512,
126113
.shader_core_count = 2,
127114
.nn_core_count = 0,
128-
.nn_mad_per_core = 0,
129-
.tp_core_count = 0,
130-
.on_chip_sram_size = 0,
131-
.axi_sram_size = 0,
132115
.vertex_cache_size = 16,
133116
.vertex_output_buffer_size = 1024,
134117
.pixel_pipes = 1,
@@ -160,11 +143,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
160143
.register_max = 64,
161144
.thread_count = 512,
162145
.shader_core_count = 2,
163-
.nn_core_count = 0,
164-
.nn_mad_per_core = 0,
165-
.tp_core_count = 0,
166-
.on_chip_sram_size = 0,
167-
.axi_sram_size = 0,
168146
.vertex_cache_size = 16,
169147
.vertex_output_buffer_size = 1024,
170148
.pixel_pipes = 1,
@@ -197,10 +175,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
197175
.thread_count = 1024,
198176
.shader_core_count = 4,
199177
.nn_core_count = 0,
200-
.nn_mad_per_core = 0,
201-
.tp_core_count = 0,
202-
.on_chip_sram_size = 0,
203-
.axi_sram_size = 0,
204178
.vertex_cache_size = 16,
205179
.vertex_output_buffer_size = 1024,
206180
.pixel_pipes = 2,
@@ -233,10 +207,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
233207
.thread_count = 256,
234208
.shader_core_count = 1,
235209
.nn_core_count = 8,
236-
.nn_mad_per_core = 64,
237-
.tp_core_count = 4,
238-
.on_chip_sram_size = 524288,
239-
.axi_sram_size = 1048576,
240210
.vertex_cache_size = 16,
241211
.vertex_output_buffer_size = 1024,
242212
.pixel_pipes = 1,
@@ -269,10 +239,6 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
269239
.thread_count = 256,
270240
.shader_core_count = 1,
271241
.nn_core_count = 6,
272-
.nn_mad_per_core = 64,
273-
.tp_core_count = 3,
274-
.on_chip_sram_size = 262144,
275-
.axi_sram_size = 0,
276242
.vertex_cache_size = 16,
277243
.vertex_output_buffer_size = 1024,
278244
.pixel_pipes = 1,

‎include/uapi/drm/etnaviv_drm.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -77,11 +77,6 @@ struct drm_etnaviv_timespec {
7777
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
7878
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
7979
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
80-
#define ETNAVIV_PARAM_GPU_NN_CORE_COUNT 0x1f
81-
#define ETNAVIV_PARAM_GPU_NN_MAD_PER_CORE 0x20
82-
#define ETNAVIV_PARAM_GPU_TP_CORE_COUNT 0x21
83-
#define ETNAVIV_PARAM_GPU_ON_CHIP_SRAM_SIZE 0x22
84-
#define ETNAVIV_PARAM_GPU_AXI_SRAM_SIZE 0x23
8580

8681
#define ETNA_MAX_PIPES 4
8782

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