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Ben Skeggsairlied
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drm/nouveau/nvjpg/r535: initial support
Adds support for allocating NVJPG classes from RM. Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/nouveau/include/nvif/cl0080.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,7 @@ struct nv_device_time_v0 {
9191
#define NV_DEVICE_HOST_RUNLIST_ENGINES_SEC2 0x00004000
9292
#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVDEC 0x00008000
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#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVENC 0x00010000
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#define NV_DEVICE_HOST_RUNLIST_ENGINES_NVJPG 0x00020000
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/* Returns the number of available channels on runlist(data). */
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#define NV_DEVICE_HOST_RUNLIST_CHANNELS NV_DEVICE_HOST(0x00000101)
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#endif

drivers/gpu/drm/nouveau/include/nvif/class.h

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Original file line numberDiff line numberDiff line change
@@ -253,4 +253,7 @@
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#define ADA_COMPUTE_A 0x0000c9c0
254254

255255
#define NV74_CIPHER 0x000074c1
256+
257+
#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
258+
#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
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#endif
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@@ -0,0 +1,8 @@
1+
/* SPDX-License-Identifier: MIT */
2+
#ifndef __NVKM_NVJPG_H__
3+
#define __NVKM_NVJPG_H__
4+
#include <core/engine.h>
5+
6+
int ga100_nvjpg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
7+
int ad102_nvjpg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
8+
#endif

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,13 @@ typedef struct
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NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2
120120
} NV_MSENC_ALLOCATION_PARAMETERS;
121121

122+
typedef struct
123+
{
124+
NvU32 size;
125+
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG?
126+
NvU32 engineInstance;
127+
} NV_NVJPG_ALLOCATION_PARAMETERS;
128+
122129
typedef struct
123130
{
124131
NvU32 index;

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h

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Original file line numberDiff line numberDiff line change
@@ -37,6 +37,11 @@
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#define MC_ENGINE_IDX_MSENC2 40
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#define MC_ENGINE_IDX_GSP 49
40+
#define MC_ENGINE_IDX_NVJPG 50
41+
#define MC_ENGINE_IDX_NVJPEG MC_ENGINE_IDX_NVJPG
42+
#define MC_ENGINE_IDX_NVJPEG0 MC_ENGINE_IDX_NVJPEG
43+
44+
#define MC_ENGINE_IDX_NVJPEG7 57
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4146
#define MC_ENGINE_IDX_BSP 64
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#define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP

drivers/gpu/drm/nouveau/nvkm/engine/Kbuild

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Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ include $(src)/nvkm/engine/msppp/Kbuild
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include $(src)/nvkm/engine/msvld/Kbuild
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include $(src)/nvkm/engine/nvenc/Kbuild
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include $(src)/nvkm/engine/nvdec/Kbuild
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include $(src)/nvkm/engine/nvjpg/Kbuild
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include $(src)/nvkm/engine/pm/Kbuild
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include $(src)/nvkm/engine/sec/Kbuild
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include $(src)/nvkm/engine/sec2/Kbuild

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

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Original file line numberDiff line numberDiff line change
@@ -2593,6 +2593,7 @@ nv170_chipset = {
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.ce = { 0x000003ff, ga100_ce_new },
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.fifo = { 0x00000001, ga100_fifo_new },
25952595
.nvdec = { 0x0000001f, ga100_nvdec_new },
2596+
.nvjpg = { 0x00000001, ga100_nvjpg_new },
25962597
};
25972598

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static const struct nvkm_device_chip
@@ -2771,6 +2772,7 @@ nv192_chipset = {
27712772
.gr = { 0x00000001, ad102_gr_new },
27722773
.nvdec = { 0x0000000f, ad102_nvdec_new },
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.nvenc = { 0x00000007, ad102_nvenc_new },
2775+
.nvjpg = { 0x0000000f, ad102_nvjpg_new },
27742776
.sec2 = { 0x00000001, ga102_sec2_new },
27752777
};
27762778

@@ -2795,6 +2797,7 @@ nv193_chipset = {
27952797
.gr = { 0x00000001, ad102_gr_new },
27962798
.nvdec = { 0x0000000f, ad102_nvdec_new },
27972799
.nvenc = { 0x00000007, ad102_nvenc_new },
2800+
.nvjpg = { 0x0000000f, ad102_nvjpg_new },
27982801
.sec2 = { 0x00000001, ga102_sec2_new },
27992802
};
28002803

@@ -2819,6 +2822,7 @@ nv194_chipset = {
28192822
.gr = { 0x00000001, ad102_gr_new },
28202823
.nvdec = { 0x0000000f, ad102_nvdec_new },
28212824
.nvenc = { 0x00000007, ad102_nvenc_new },
2825+
.nvjpg = { 0x0000000f, ad102_nvjpg_new },
28222826
.sec2 = { 0x00000001, ga102_sec2_new },
28232827
};
28242828

@@ -2843,6 +2847,7 @@ nv196_chipset = {
28432847
.gr = { 0x00000001, ad102_gr_new },
28442848
.nvdec = { 0x0000000f, ad102_nvdec_new },
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.nvenc = { 0x00000007, ad102_nvenc_new },
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.nvjpg = { 0x0000000f, ad102_nvjpg_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
28472852
};
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@@ -2867,6 +2872,7 @@ nv197_chipset = {
28672872
.gr = { 0x00000001, ad102_gr_new },
28682873
.nvdec = { 0x0000000f, ad102_nvdec_new },
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.nvenc = { 0x00000007, ad102_nvenc_new },
2875+
.nvjpg = { 0x0000000f, ad102_nvjpg_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
28712877
};
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drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h

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@@ -43,6 +43,7 @@
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#include <engine/msvld.h>
4444
#include <engine/nvenc.h>
4545
#include <engine/nvdec.h>
46+
#include <engine/nvjpg.h>
4647
#include <engine/pm.h>
4748
#include <engine/sec.h>
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#include <engine/sec2.h>

drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c

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@@ -210,6 +210,7 @@ nvkm_fifo_info(struct nvkm_engine *engine, u64 mthd, u64 *data)
210210
CASE(SEC2 );
211211
CASE(NVDEC );
212212
CASE(NVENC );
213+
CASE(NVJPG );
213214
default:
214215
WARN_ON(1);
215216
break;

drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c

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@@ -597,6 +597,7 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
597597
break;
598598
case NVKM_ENGINE_NVDEC:
599599
case NVKM_ENGINE_NVENC:
600+
case NVKM_ENGINE_NVJPG:
600601
engn = nvkm_runl_add(runl, nv2080, &r535_flcn, type, inst);
601602
break;
602603
case NVKM_ENGINE_SW:

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