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38 | 38 | #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
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39 | 39 | #define I2C_IO_CONFIG_PUSH_PULL 0x0000
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40 | 40 | #define I2C_SOFT_RST 0x0001
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| 41 | +#define I2C_HANDSHAKE_RST 0x0020 |
41 | 42 | #define I2C_FIFO_ADDR_CLR 0x0001
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42 | 43 | #define I2C_DELAY_LEN 0x0002
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43 | 44 | #define I2C_TIME_CLR_VALUE 0x0000
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44 | 45 | #define I2C_TIME_DEFAULT_VALUE 0x0003
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45 | 46 | #define I2C_WRRD_TRANAC_VALUE 0x0002
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46 | 47 | #define I2C_RD_TRANAC_VALUE 0x0001
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47 | 48 | #define I2C_SCL_MIS_COMP_VALUE 0x0000
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| 49 | +#define I2C_CHN_CLR_FLAG 0x0000 |
48 | 50 |
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49 | 51 | #define I2C_DMA_CON_TX 0x0000
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50 | 52 | #define I2C_DMA_CON_RX 0x0001
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54 | 56 | #define I2C_DMA_START_EN 0x0001
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55 | 57 | #define I2C_DMA_INT_FLAG_NONE 0x0000
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56 | 58 | #define I2C_DMA_CLR_FLAG 0x0000
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| 59 | +#define I2C_DMA_WARM_RST 0x0001 |
57 | 60 | #define I2C_DMA_HARD_RST 0x0002
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| 61 | +#define I2C_DMA_HANDSHAKE_RST 0x0004 |
58 | 62 |
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59 | 63 | #define MAX_SAMPLE_CNT_DIV 8
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60 | 64 | #define MAX_STEP_CNT_DIV 64
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@@ -475,11 +479,24 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
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475 | 479 | {
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476 | 480 | u16 control_reg;
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477 | 481 |
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478 |
| - writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); |
479 |
| - udelay(50); |
480 |
| - writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); |
481 |
| - |
482 |
| - mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); |
| 482 | + if (i2c->dev_comp->dma_sync) { |
| 483 | + writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); |
| 484 | + udelay(10); |
| 485 | + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); |
| 486 | + udelay(10); |
| 487 | + writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, |
| 488 | + i2c->pdmabase + OFFSET_RST); |
| 489 | + mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, |
| 490 | + OFFSET_SOFTRESET); |
| 491 | + udelay(10); |
| 492 | + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); |
| 493 | + mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); |
| 494 | + } else { |
| 495 | + writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); |
| 496 | + udelay(50); |
| 497 | + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); |
| 498 | + mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); |
| 499 | + } |
483 | 500 |
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484 | 501 | /* Set ioconfig */
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485 | 502 | if (i2c->use_push_pull)
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