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Joshua YeongConchuOD
Joshua Yeong
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ConchuOD
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cache: Add StarFive StarLink cache management
Add StarFive Starlink cache management driver. The driver enables RISC-V non-standard cache operation on SoC that does not support Zicbom extension instructions. Signed-off-by: Joshua Yeong <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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3 files changed

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‎drivers/cache/Kconfig

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@@ -14,4 +14,13 @@ config SIFIVE_CCACHE
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help
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Support for the composable cache controller on SiFive platforms.
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config STARFIVE_STARLINK_CACHE
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bool "StarFive StarLink Cache controller"
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depends on RISCV
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depends on ARCH_STARFIVE
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the StarLink cache controller IP from StarFive.
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endmenu

‎drivers/cache/Makefile

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@@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
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obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
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obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
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obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
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obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o

‎drivers/cache/starfive_starlink_cache.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Cache Management Operations for StarFive's Starlink cache controller
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*
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* Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
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*
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* Author: Joshua Yeong <[email protected]>
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*/
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#include <linux/bitfield.h>
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#include <linux/cacheflush.h>
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#include <linux/iopoll.h>
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#include <linux/of_address.h>
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#include <asm/dma-noncoherent.h>
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#define STARLINK_CACHE_FLUSH_START_ADDR 0x0
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#define STARLINK_CACHE_FLUSH_END_ADDR 0x8
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#define STARLINK_CACHE_FLUSH_CTL 0x10
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#define STARLINK_CACHE_ALIGN 0x40
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#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0)
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#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1)
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#define STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK BIT(0)
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#define STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE 0
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#define STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE 1
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#define STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED 2
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#define STARLINK_CACHE_FLUSH_POLL_DELAY_US 1
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#define STARLINK_CACHE_FLUSH_TIMEOUT_US 5000000
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static void __iomem *starlink_cache_base;
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static void starlink_cache_flush_complete(void)
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{
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volatile void __iomem *ctl = starlink_cache_base + STARLINK_CACHE_FLUSH_CTL;
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u64 v;
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int ret;
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ret = readq_poll_timeout_atomic(ctl, v, !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK),
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STARLINK_CACHE_FLUSH_POLL_DELAY_US,
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STARLINK_CACHE_FLUSH_TIMEOUT_US);
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if (ret)
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WARN(1, "StarFive Starlink cache flush operation timeout\n");
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}
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static void starlink_cache_dma_cache_wback(phys_addr_t paddr, unsigned long size)
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{
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
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STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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starlink_cache_flush_complete();
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}
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static void starlink_cache_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
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{
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
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STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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starlink_cache_flush_complete();
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}
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static void starlink_cache_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
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{
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
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starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
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writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
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starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
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mb();
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writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
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STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE),
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starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
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starlink_cache_flush_complete();
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}
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static const struct riscv_nonstd_cache_ops starlink_cache_ops = {
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.wback = &starlink_cache_dma_cache_wback,
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.inv = &starlink_cache_dma_cache_invalidate,
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.wback_inv = &starlink_cache_dma_cache_wback_inv,
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};
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static const struct of_device_id starlink_cache_ids[] = {
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{ .compatible = "starfive,jh8100-starlink-cache" },
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{ /* sentinel */ }
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};
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static int __init starlink_cache_init(void)
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{
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struct device_node *np;
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u32 block_size;
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int ret;
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np = of_find_matching_node(NULL, starlink_cache_ids);
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if (!of_device_is_available(np))
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return -ENODEV;
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ret = of_property_read_u32(np, "cache-block-size", &block_size);
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if (ret)
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return ret;
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if (block_size % STARLINK_CACHE_ALIGN)
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return -EINVAL;
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starlink_cache_base = of_iomap(np, 0);
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if (!starlink_cache_base)
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return -ENOMEM;
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riscv_cbom_block_size = block_size;
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riscv_noncoherent_supported();
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riscv_noncoherent_register_cache_ops(&starlink_cache_ops);
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return 0;
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}
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arch_initcall(starlink_cache_init);

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