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airliedairlied
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Merge tag 'amd-drm-next-5.17-2021-12-30' of ssh://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.17-2021-12-30: amdgpu: - Suspend/resume fixes - Fence fix - Misc code cleanups - IP discovery fixes - SRIOV fixes - RAS fixes - GMC 8 VRAM detection fix - FRU fixes for Aldebaran - Display fixes amdkfd: - SVM fixes - IP discovery fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 011e8c3 + 0637d41 commit cb6846f

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83 files changed

+1814
-747
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -812,6 +812,7 @@ struct amd_powerplay {
812812

813813
#define AMDGPU_RESET_MAGIC_NUM 64
814814
#define AMDGPU_MAX_DF_PERFMONS 4
815+
#define AMDGPU_PRODUCT_NAME_LEN 64
815816
struct amdgpu_device {
816817
struct device *dev;
817818
struct pci_dev *pdev;
@@ -1082,7 +1083,7 @@ struct amdgpu_device {
10821083

10831084
/* Chip product information */
10841085
char product_number[16];
1085-
char product_name[32];
1086+
char product_name[AMDGPU_PRODUCT_NAME_LEN];
10861087
char serial[20];
10871088

10881089
atomic_t throttling_logging_enabled;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -721,13 +721,13 @@ bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
721721
return adev->have_atomics_support;
722722
}
723723

724-
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev)
724+
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
725725
{
726726
struct ras_err_data err_data = {0, 0, 0, NULL};
727727

728728
/* CPU MCA will handle page retirement if connected_to_cpu is 1 */
729729
if (!adev->gmc.xgmi.connected_to_cpu)
730-
amdgpu_umc_process_ras_data_cb(adev, &err_data, NULL);
731-
else
730+
amdgpu_umc_poison_handler(adev, &err_data, reset);
731+
else if (reset)
732732
amdgpu_amdkfd_gpu_reset(adev);
733733
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
296296
uint64_t *mmap_offset);
297297
int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
298298
struct tile_config *config);
299-
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev);
299+
void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
300+
bool reset);
300301
#if IS_ENABLED(CONFIG_HSA_AMD)
301302
void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
302303
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)
166166

167167
lock_srbm(adev, mec, pipe, 0, 0);
168168

169-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
169+
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
170170
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
171171
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
172172

@@ -279,7 +279,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,
279279
lower_32_bits((uintptr_t)wptr));
280280
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
281281
upper_32_bits((uintptr_t)wptr));
282-
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
282+
WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
283283
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
284284
}
285285

@@ -488,13 +488,13 @@ bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
488488
uint32_t low, high;
489489

490490
acquire_queue(adev, pipe_id, queue_id);
491-
act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
491+
act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
492492
if (act) {
493493
low = lower_32_bits(queue_address >> 8);
494494
high = upper_32_bits(queue_address >> 8);
495495

496-
if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
497-
high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
496+
if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
497+
high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
498498
retval = true;
499499
}
500500
release_queue(adev);
@@ -556,7 +556,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
556556

557557
end_jiffies = (utimeout * HZ / 1000) + jiffies;
558558
while (true) {
559-
temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
559+
temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
560560
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
561561
break;
562562
if (time_after(jiffies, end_jiffies)) {
@@ -645,7 +645,7 @@ int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
645645
mutex_lock(&adev->grbm_idx_mutex);
646646

647647
WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
648-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
648+
WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
649649

650650
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
651651
INSTANCE_BROADCAST_WRITES, 1);
@@ -722,7 +722,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,
722722
pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;
723723
queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;
724724
soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);
725-
reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
725+
reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +
726726
queue_slot);
727727
*wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;
728728
if (*wave_cnt != 0)
@@ -809,8 +809,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
809809
for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {
810810

811811
gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);
812-
queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,
813-
mmSPI_CSQ_WF_ACTIVE_STATUS));
812+
queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);
814813

815814
/*
816815
* Assumption: queue map encodes following schema: four
@@ -860,17 +859,17 @@ void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
860859
/*
861860
* Program TBA registers
862861
*/
863-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
862+
WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO,
864863
lower_32_bits(tba_addr >> 8));
865-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
864+
WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI,
866865
upper_32_bits(tba_addr >> 8));
867866

868867
/*
869868
* Program TMA registers
870869
*/
871-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
870+
WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO,
872871
lower_32_bits(tma_addr >> 8));
873-
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
872+
WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_HI,
874873
upper_32_bits(tma_addr >> 8));
875874

876875
unlock_srbm(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 29 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2317,6 +2317,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
23172317

23182318
/* need to do gmc hw init early so we can allocate gpu mem */
23192319
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2320+
/* Try to reserve bad pages early */
2321+
if (amdgpu_sriov_vf(adev))
2322+
amdgpu_virt_exchange_data(adev);
2323+
23202324
r = amdgpu_device_vram_scratch_init(adev);
23212325
if (r) {
23222326
DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
@@ -2348,7 +2352,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
23482352
}
23492353

23502354
if (amdgpu_sriov_vf(adev))
2351-
amdgpu_virt_init_data_exchange(adev);
2355+
amdgpu_virt_exchange_data(adev);
23522356

23532357
r = amdgpu_ib_pool_init(adev);
23542358
if (r) {
@@ -2615,11 +2619,10 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
26152619
if (r)
26162620
DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
26172621

2618-
/* For XGMI + passthrough configuration on arcturus, enable light SBR */
2619-
if (adev->asic_type == CHIP_ARCTURUS &&
2620-
amdgpu_passthrough(adev) &&
2621-
adev->gmc.xgmi.num_physical_nodes > 1)
2622-
smu_set_light_sbr(&adev->smu, true);
2622+
/* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2623+
if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
2624+
adev->asic_type == CHIP_ALDEBARAN ))
2625+
smu_handle_passthrough_sbr(&adev->smu, true);
26232626

26242627
if (adev->gmc.xgmi.num_physical_nodes > 1) {
26252628
mutex_lock(&mgpu_info.mutex);
@@ -3182,6 +3185,12 @@ static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
31823185
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
31833186
{
31843187
switch (asic_type) {
3188+
#ifdef CONFIG_DRM_AMDGPU_SI
3189+
case CHIP_HAINAN:
3190+
#endif
3191+
case CHIP_TOPAZ:
3192+
/* chips with no display hardware */
3193+
return false;
31853194
#if defined(CONFIG_DRM_AMD_DC)
31863195
case CHIP_TAHITI:
31873196
case CHIP_PITCAIRN:
@@ -3573,6 +3582,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
35733582
if (r)
35743583
return r;
35753584

3585+
/* Need to get xgmi info early to decide the reset behavior*/
3586+
if (adev->gmc.xgmi.supported) {
3587+
r = adev->gfxhub.funcs->get_xgmi_info(adev);
3588+
if (r)
3589+
return r;
3590+
}
3591+
35763592
/* enable PCIE atomic ops */
35773593
if (amdgpu_sriov_vf(adev))
35783594
adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
@@ -3885,11 +3901,14 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
38853901

38863902
amdgpu_irq_fini_hw(adev);
38873903

3888-
ttm_device_clear_dma_mappings(&adev->mman.bdev);
3904+
if (adev->mman.initialized)
3905+
ttm_device_clear_dma_mappings(&adev->mman.bdev);
38893906

38903907
amdgpu_gart_dummy_page_fini(adev);
38913908

3892-
amdgpu_device_unmap_mmio(adev);
3909+
if (drm_dev_is_unplugged(adev_to_drm(adev)))
3910+
amdgpu_device_unmap_mmio(adev);
3911+
38933912
}
38943913

38953914
void amdgpu_device_fini_sw(struct amdgpu_device *adev)
@@ -4507,7 +4526,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
45074526
int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
45084527
struct amdgpu_reset_context *reset_context)
45094528
{
4510-
int i, j, r = 0;
4529+
int i, r = 0;
45114530
struct amdgpu_job *job = NULL;
45124531
bool need_full_reset =
45134532
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
@@ -4529,15 +4548,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
45294548

45304549
/*clear job fence from fence drv to avoid force_completion
45314550
*leave NULL and vm flush fence in fence drv */
4532-
for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {
4533-
struct dma_fence *old, **ptr;
4551+
amdgpu_fence_driver_clear_job_fences(ring);
45344552

4535-
ptr = &ring->fence_drv.fences[j];
4536-
old = rcu_dereference_protected(*ptr, 1);
4537-
if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
4538-
RCU_INIT_POINTER(*ptr, NULL);
4539-
}
4540-
}
45414553
/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
45424554
amdgpu_fence_driver_force_completion(ring);
45434555
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 55 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -565,39 +565,71 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
565565
}
566566
}
567567

568+
union gc_info {
569+
struct gc_info_v1_0 v1;
570+
struct gc_info_v2_0 v2;
571+
};
572+
568573
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
569574
{
570575
struct binary_header *bhdr;
571-
struct gc_info_v1_0 *gc_info;
576+
union gc_info *gc_info;
572577

573578
if (!adev->mman.discovery_bin) {
574579
DRM_ERROR("ip discovery uninitialized\n");
575580
return -EINVAL;
576581
}
577582

578583
bhdr = (struct binary_header *)adev->mman.discovery_bin;
579-
gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
584+
gc_info = (union gc_info *)(adev->mman.discovery_bin +
580585
le16_to_cpu(bhdr->table_list[GC].offset));
581-
582-
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
583-
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
584-
le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
585-
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
586-
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
587-
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
588-
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
589-
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
590-
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
591-
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
592-
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
593-
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
594-
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
595-
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
596-
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
597-
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
598-
le32_to_cpu(gc_info->gc_num_sa_per_se);
599-
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
600-
586+
switch (gc_info->v1.header.version_major) {
587+
case 1:
588+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
589+
adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
590+
le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
591+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
592+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
593+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
594+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
595+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
596+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
597+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
598+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
599+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
600+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
601+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
602+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
603+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
604+
le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
605+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
606+
break;
607+
case 2:
608+
adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
609+
adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
610+
adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
611+
adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
612+
adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
613+
adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
614+
adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
615+
adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
616+
adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
617+
adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
618+
adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
619+
adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
620+
adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
621+
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
622+
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
623+
le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
624+
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
625+
break;
626+
default:
627+
dev_err(adev->dev,
628+
"Unhandled GC info table %d.%d\n",
629+
gc_info->v1.header.version_major,
630+
gc_info->v1.header.version_minor);
631+
return -EINVAL;
632+
}
601633
return 0;
602634
}
603635

@@ -992,7 +1024,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
9921024
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
9931025
break;
9941026
default:
995-
break;;
1027+
break;
9961028
}
9971029
return 0;
9981030
}

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