@@ -234,6 +234,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
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ARM64_FTR_END ,
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};
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+ static const struct arm64_ftr_bits ftr_id_aa64isar3 [] = {
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+ ARM64_FTR_END ,
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+ };
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+
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static const struct arm64_ftr_bits ftr_id_aa64pfr0 [] = {
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ARM64_FTR_BITS (FTR_HIDDEN , FTR_NONSTRICT , FTR_LOWER_SAFE , ID_AA64PFR0_EL1_CSV3_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_HIDDEN , FTR_NONSTRICT , FTR_LOWER_SAFE , ID_AA64PFR0_EL1_CSV2_SHIFT , 4 , 0 ),
@@ -267,6 +271,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
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ARM64_FTR_END ,
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};
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+ static const struct arm64_ftr_bits ftr_id_aa64pfr2 [] = {
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+ ARM64_FTR_END ,
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+ };
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+
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static const struct arm64_ftr_bits ftr_id_aa64zfr0 [] = {
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_F64MM_SHIFT , 4 , 0 ),
@@ -319,6 +327,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
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ARM64_FTR_END ,
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};
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+ static const struct arm64_ftr_bits ftr_id_aa64fpfr0 [] = {
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+ ARM64_FTR_END ,
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+ };
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+
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static const struct arm64_ftr_bits ftr_id_aa64mmfr0 [] = {
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_LOWER_SAFE , ID_AA64MMFR0_EL1_ECV_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_HIDDEN , FTR_STRICT , FTR_LOWER_SAFE , ID_AA64MMFR0_EL1_FGT_SHIFT , 4 , 0 ),
@@ -702,10 +714,12 @@ static const struct __ftr_reg_entry {
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& id_aa64pfr0_override ),
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ARM64_FTR_REG_OVERRIDE (SYS_ID_AA64PFR1_EL1 , ftr_id_aa64pfr1 ,
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& id_aa64pfr1_override ),
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+ ARM64_FTR_REG (SYS_ID_AA64PFR2_EL1 , ftr_id_aa64pfr2 ),
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ARM64_FTR_REG_OVERRIDE (SYS_ID_AA64ZFR0_EL1 , ftr_id_aa64zfr0 ,
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& id_aa64zfr0_override ),
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ARM64_FTR_REG_OVERRIDE (SYS_ID_AA64SMFR0_EL1 , ftr_id_aa64smfr0 ,
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& id_aa64smfr0_override ),
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+ ARM64_FTR_REG (SYS_ID_AA64FPFR0_EL1 , ftr_id_aa64fpfr0 ),
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/* Op1 = 0, CRn = 0, CRm = 5 */
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ARM64_FTR_REG (SYS_ID_AA64DFR0_EL1 , ftr_id_aa64dfr0 ),
@@ -717,6 +731,7 @@ static const struct __ftr_reg_entry {
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& id_aa64isar1_override ),
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ARM64_FTR_REG_OVERRIDE (SYS_ID_AA64ISAR2_EL1 , ftr_id_aa64isar2 ,
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& id_aa64isar2_override ),
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+ ARM64_FTR_REG (SYS_ID_AA64ISAR3_EL1 , ftr_id_aa64isar3 ),
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/* Op1 = 0, CRn = 0, CRm = 7 */
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ARM64_FTR_REG (SYS_ID_AA64MMFR0_EL1 , ftr_id_aa64mmfr0 ),
@@ -1043,14 +1058,17 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
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init_cpu_ftr_reg (SYS_ID_AA64ISAR0_EL1 , info -> reg_id_aa64isar0 );
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init_cpu_ftr_reg (SYS_ID_AA64ISAR1_EL1 , info -> reg_id_aa64isar1 );
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init_cpu_ftr_reg (SYS_ID_AA64ISAR2_EL1 , info -> reg_id_aa64isar2 );
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+ init_cpu_ftr_reg (SYS_ID_AA64ISAR3_EL1 , info -> reg_id_aa64isar3 );
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init_cpu_ftr_reg (SYS_ID_AA64MMFR0_EL1 , info -> reg_id_aa64mmfr0 );
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init_cpu_ftr_reg (SYS_ID_AA64MMFR1_EL1 , info -> reg_id_aa64mmfr1 );
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init_cpu_ftr_reg (SYS_ID_AA64MMFR2_EL1 , info -> reg_id_aa64mmfr2 );
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init_cpu_ftr_reg (SYS_ID_AA64MMFR3_EL1 , info -> reg_id_aa64mmfr3 );
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init_cpu_ftr_reg (SYS_ID_AA64PFR0_EL1 , info -> reg_id_aa64pfr0 );
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init_cpu_ftr_reg (SYS_ID_AA64PFR1_EL1 , info -> reg_id_aa64pfr1 );
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+ init_cpu_ftr_reg (SYS_ID_AA64PFR2_EL1 , info -> reg_id_aa64pfr2 );
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init_cpu_ftr_reg (SYS_ID_AA64ZFR0_EL1 , info -> reg_id_aa64zfr0 );
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init_cpu_ftr_reg (SYS_ID_AA64SMFR0_EL1 , info -> reg_id_aa64smfr0 );
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+ init_cpu_ftr_reg (SYS_ID_AA64FPFR0_EL1 , info -> reg_id_aa64fpfr0 );
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if (id_aa64pfr0_32bit_el0 (info -> reg_id_aa64pfr0 ))
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init_32bit_cpu_features (& info -> aarch32 );
@@ -1272,6 +1290,8 @@ void update_cpu_features(int cpu,
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info -> reg_id_aa64isar1 , boot -> reg_id_aa64isar1 );
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taint |= check_update_ftr_reg (SYS_ID_AA64ISAR2_EL1 , cpu ,
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info -> reg_id_aa64isar2 , boot -> reg_id_aa64isar2 );
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+ taint |= check_update_ftr_reg (SYS_ID_AA64ISAR3_EL1 , cpu ,
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+ info -> reg_id_aa64isar3 , boot -> reg_id_aa64isar3 );
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/*
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* Differing PARange support is fine as long as all peripherals and
@@ -1291,13 +1311,18 @@ void update_cpu_features(int cpu,
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info -> reg_id_aa64pfr0 , boot -> reg_id_aa64pfr0 );
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taint |= check_update_ftr_reg (SYS_ID_AA64PFR1_EL1 , cpu ,
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info -> reg_id_aa64pfr1 , boot -> reg_id_aa64pfr1 );
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+ taint |= check_update_ftr_reg (SYS_ID_AA64PFR2_EL1 , cpu ,
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+ info -> reg_id_aa64pfr2 , boot -> reg_id_aa64pfr2 );
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taint |= check_update_ftr_reg (SYS_ID_AA64ZFR0_EL1 , cpu ,
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info -> reg_id_aa64zfr0 , boot -> reg_id_aa64zfr0 );
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taint |= check_update_ftr_reg (SYS_ID_AA64SMFR0_EL1 , cpu ,
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info -> reg_id_aa64smfr0 , boot -> reg_id_aa64smfr0 );
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+ taint |= check_update_ftr_reg (SYS_ID_AA64FPFR0_EL1 , cpu ,
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+ info -> reg_id_aa64fpfr0 , boot -> reg_id_aa64fpfr0 );
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+
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/* Probe vector lengths */
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if (IS_ENABLED (CONFIG_ARM64_SVE ) &&
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id_aa64pfr0_sve (read_sanitised_ftr_reg (SYS_ID_AA64PFR0_EL1 ))) {
@@ -1410,8 +1435,10 @@ u64 __read_sysreg_by_encoding(u32 sys_id)
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read_sysreg_case (SYS_ID_AA64PFR0_EL1 );
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read_sysreg_case (SYS_ID_AA64PFR1_EL1 );
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+ read_sysreg_case (SYS_ID_AA64PFR2_EL1 );
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read_sysreg_case (SYS_ID_AA64ZFR0_EL1 );
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read_sysreg_case (SYS_ID_AA64SMFR0_EL1 );
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+ read_sysreg_case (SYS_ID_AA64FPFR0_EL1 );
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read_sysreg_case (SYS_ID_AA64DFR0_EL1 );
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read_sysreg_case (SYS_ID_AA64DFR1_EL1 );
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read_sysreg_case (SYS_ID_AA64MMFR0_EL1 );
@@ -1421,6 +1448,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id)
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read_sysreg_case (SYS_ID_AA64ISAR0_EL1 );
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read_sysreg_case (SYS_ID_AA64ISAR1_EL1 );
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read_sysreg_case (SYS_ID_AA64ISAR2_EL1 );
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+ read_sysreg_case (SYS_ID_AA64ISAR3_EL1 );
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read_sysreg_case (SYS_CNTFRQ_EL0 );
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read_sysreg_case (SYS_CTR_EL0 );
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