|
103 | 103 | "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", |
104 | 104 | "MetricName": "tma_backend_bound", |
105 | 105 | "MetricThreshold": "tma_backend_bound > 0.2", |
| 106 | + "MetricgroupNoGroup": "TopdownL1", |
106 | 107 | "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", |
107 | 108 | "ScaleUnit": "100%" |
108 | 109 | }, |
|
112 | 113 | "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", |
113 | 114 | "MetricName": "tma_bad_speculation", |
114 | 115 | "MetricThreshold": "tma_bad_speculation > 0.15", |
| 116 | + "MetricgroupNoGroup": "TopdownL1", |
115 | 117 | "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", |
116 | 118 | "ScaleUnit": "100%" |
117 | 119 | }, |
|
122 | 124 | "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", |
123 | 125 | "MetricName": "tma_branch_mispredicts", |
124 | 126 | "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", |
| 127 | + "MetricgroupNoGroup": "TopdownL2", |
125 | 128 | "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", |
126 | 129 | "ScaleUnit": "100%" |
127 | 130 | }, |
|
170 | 173 | "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", |
171 | 174 | "MetricName": "tma_core_bound", |
172 | 175 | "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", |
| 176 | + "MetricgroupNoGroup": "TopdownL2", |
173 | 177 | "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", |
174 | 178 | "ScaleUnit": "100%" |
175 | 179 | }, |
|
263 | 267 | "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", |
264 | 268 | "MetricName": "tma_fetch_bandwidth", |
265 | 269 | "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", |
| 270 | + "MetricgroupNoGroup": "TopdownL2", |
266 | 271 | "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", |
267 | 272 | "ScaleUnit": "100%" |
268 | 273 | }, |
|
272 | 277 | "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", |
273 | 278 | "MetricName": "tma_fetch_latency", |
274 | 279 | "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", |
| 280 | + "MetricgroupNoGroup": "TopdownL2", |
275 | 281 | "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", |
276 | 282 | "ScaleUnit": "100%" |
277 | 283 | }, |
|
326 | 332 | "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", |
327 | 333 | "MetricName": "tma_frontend_bound", |
328 | 334 | "MetricThreshold": "tma_frontend_bound > 0.15", |
| 335 | + "MetricgroupNoGroup": "TopdownL1", |
329 | 336 | "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", |
330 | 337 | "ScaleUnit": "100%" |
331 | 338 | }, |
|
335 | 342 | "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", |
336 | 343 | "MetricName": "tma_heavy_operations", |
337 | 344 | "MetricThreshold": "tma_heavy_operations > 0.1", |
| 345 | + "MetricgroupNoGroup": "TopdownL2", |
338 | 346 | "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", |
339 | 347 | "ScaleUnit": "100%" |
340 | 348 | }, |
|
828 | 836 | "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", |
829 | 837 | "MetricName": "tma_light_operations", |
830 | 838 | "MetricThreshold": "tma_light_operations > 0.6", |
| 839 | + "MetricgroupNoGroup": "TopdownL2", |
831 | 840 | "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", |
832 | 841 | "ScaleUnit": "100%" |
833 | 842 | }, |
|
858 | 867 | "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", |
859 | 868 | "MetricName": "tma_machine_clears", |
860 | 869 | "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", |
| 870 | + "MetricgroupNoGroup": "TopdownL2", |
861 | 871 | "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", |
862 | 872 | "ScaleUnit": "100%" |
863 | 873 | }, |
|
886 | 896 | "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", |
887 | 897 | "MetricName": "tma_memory_bound", |
888 | 898 | "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", |
| 899 | + "MetricgroupNoGroup": "TopdownL2", |
889 | 900 | "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", |
890 | 901 | "ScaleUnit": "100%" |
891 | 902 | }, |
|
1048 | 1059 | "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", |
1049 | 1060 | "MetricName": "tma_retiring", |
1050 | 1061 | "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", |
| 1062 | + "MetricgroupNoGroup": "TopdownL1", |
1051 | 1063 | "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", |
1052 | 1064 | "ScaleUnit": "100%" |
1053 | 1065 | }, |
|
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