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Merge branch 'remotes/lorenzo/pci/qcom'
- Add Qualcomm PCIe Endpoint controller driver and DT binding (Manivannan Sadhasivam) - Add qcom struct for device-specific details in match data (Prasad Malisetty) - Switch pcie_1_pipe_clk_src from TCXO to pipe clock after PHY init in SC7280 (Prasad Malisetty) - Add .compatible device ID for SC8180x platform (Bjorn Andersson) * remotes/lorenzo/pci/qcom: PCI: qcom: Add sc8180x compatible PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 PCI: qcom: Replace ops with struct pcie_cfg in pcie match data MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller
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‎Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCIe Endpoint Controller binding
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maintainers:
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- Manivannan Sadhasivam <[email protected]>
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allOf:
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- $ref: "pci-ep.yaml#"
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properties:
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compatible:
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const: qcom,sdx55-pcie-ep
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reg:
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items:
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- description: Qualcomm-specific PARF configuration registers
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- description: DesignWare PCIe registers
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- description: External local bus interface registers
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- description: Address Translation Unit (ATU) registers
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- description: Memory region used to map remote RC address space
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- description: BAR memory region
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reg-names:
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: atu
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- const: addr_space
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- const: mmio
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe Sleep clock
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- description: PCIe Reference clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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- const: sleep
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- const: ref
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qcom,perst-regs:
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description: Reference to a syscon representing TCSR followed by the two
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offsets within syscon for Perst enable and Perst separation
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enable registers
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$ref: "/schemas/types.yaml#/definitions/phandle-array"
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items:
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minItems: 3
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maxItems: 3
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interrupts:
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items:
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- description: PCIe Global interrupt
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- description: PCIe Doorbell interrupt
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interrupt-names:
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items:
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- const: global
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- const: doorbell
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reset-gpios:
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description: GPIO used as PERST# input signal
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maxItems: 1
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wake-gpios:
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description: GPIO used as WAKE# output signal
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: core
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power-domains:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pciephy
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num-lanes:
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default: 2
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- qcom,perst-regs
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- interrupts
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- interrupt-names
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- reset-gpios
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- resets
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- reset-names
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@40000000 {
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compatible = "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xc8>,
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<0x40001000 0x1000>,
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<0x40002000 0x1000>,
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<0x01c03000 0x3000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio";
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clocks = <&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>;
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clock-names = "aux", "cfg", "bus_master", "bus_slave",
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"slave_q2a", "sleep", "ref";
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qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell";
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie0_lane>;
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phy-names = "pciephy";
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max-link-speed = <3>;
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num-lanes = <2>;
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};

‎Documentation/devicetree/bindings/pci/qcom,pcie.txt

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- "qcom,pcie-ipq4019" for ipq4019
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- "qcom,pcie-ipq8074" for ipq8074
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- "qcom,pcie-qcs404" for qcs404
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- "qcom,pcie-sc8180x" for sc8180x
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- "qcom,pcie-sdm845" for sdm845
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- "qcom,pcie-sm8250" for sm8250
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- "qcom,pcie-ipq6018" for ipq6018
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- "pipe" PIPE clock
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- clock-names:
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Usage: required for sm8250
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Usage: required for sc8180x and sm8250
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "ahb" AHB reset
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- reset-names:
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Usage: required for sdm845 and sm8250
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Usage: required for sc8180x, sdm845 and sm8250
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pci" PCIe core reset

‎MAINTAINERS

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L: [email protected]
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L: [email protected]
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S: Maintained
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F: drivers/pci/controller/dwc/*qcom*
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F: drivers/pci/controller/dwc/pcie-qcom.c
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PCIE ENDPOINT DRIVER FOR QUALCOMM
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M: Manivannan Sadhasivam <[email protected]>
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L: [email protected]
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L: [email protected]
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S: Maintained
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F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
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F: drivers/pci/controller/dwc/pcie-qcom-ep.c
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PCIE DRIVER FOR ROCKCHIP
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M: Shawn Lin <[email protected]>

‎drivers/pci/controller/dwc/Kconfig

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PCIe controller uses the DesignWare core plus Qualcomm-specific
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hardware wrappers.
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config PCIE_QCOM_EP
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tristate "Qualcomm PCIe controller - Endpoint mode"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here to enable support for the PCIe controllers on Qualcomm SoCs
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to work in endpoint mode. The PCIe controller uses the DesignWare core
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plus Qualcomm-specific hardware wrappers.
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config PCIE_ARMADA_8K
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bool "Marvell Armada-8K PCIe controller"
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depends on ARCH_MVEBU || COMPILE_TEST

‎drivers/pci/controller/dwc/Makefile

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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o

‎drivers/pci/controller/dwc/pcie-designware-ep.c

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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
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int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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u8 interrupt_num)
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return 0;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq);
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int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
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u16 interrupt_num)

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