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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and resets on RZ/V2M - Add display clocks on R-Car V4H - Add Camera Receiving Unit (CRU) clocks and resets on RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries
2 parents 1b929c0 + fbfd614 commit ce45dff

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5 files changed

+114
-7
lines changed

5 files changed

+114
-7
lines changed

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
145145
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
146146
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
147147
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
148+
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
149+
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
148150

149151
DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
150152
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
@@ -161,6 +163,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
161163
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
162164
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
163165
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
166+
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
167+
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
168+
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
169+
DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
170+
DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
164171
DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
165172
DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
166173
DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
@@ -193,6 +200,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
193200
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
194201
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
195202
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
203+
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
204+
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
196205
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
197206
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
198207
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
@@ -211,20 +220,20 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
211220
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
212221
* 14 13 (MHz)
213222
* ------------------------------------------------------------------------
214-
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15
223+
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
215224
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
216225
* 1 0 Prohibited setting
217-
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38
226+
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
218227
*/
219228
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
220229
(((md) & BIT(13)) >> 13))
221230

222231
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
223232
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
224-
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 15, },
233+
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
225234
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
226235
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
227-
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 38, },
236+
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
228237
};
229238

230239
static int __init r8a779g0_cpg_mssr_init(struct device *dev)

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ static const struct {
182182
};
183183

184184
static const struct {
185-
struct rzg2l_mod_clk common[75];
185+
struct rzg2l_mod_clk common[79];
186186
#ifdef CONFIG_CLK_R9A07G054
187187
struct rzg2l_mod_clk drp[0];
188188
#endif
@@ -250,6 +250,14 @@ static const struct {
250250
0x558, 1),
251251
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
252252
0x558, 2),
253+
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
254+
0x564, 0),
255+
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
256+
0x564, 1),
257+
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
258+
0x564, 2),
259+
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
260+
0x564, 3),
253261
DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
254262
0x568, 0),
255263
DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
@@ -368,6 +376,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
368376
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
369377
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
370378
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
379+
DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
380+
DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
381+
DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
371382
DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
372383
DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
373384
DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
@@ -412,6 +423,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
412423
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
413424
};
414425

426+
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
427+
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
428+
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
429+
};
430+
415431
#ifdef CONFIG_CLK_R9A07G044
416432
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
417433
/* Core Clocks */
@@ -429,6 +445,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
429445
.num_mod_clks = ARRAY_SIZE(mod_clks.common),
430446
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
431447

448+
/* No PM Module Clocks */
449+
.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
450+
.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
451+
432452
/* Resets */
433453
.resets = r9a07g044_resets,
434454
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
@@ -454,6 +474,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
454474
.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
455475
.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
456476

477+
/* No PM Module Clocks */
478+
.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
479+
.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
480+
457481
/* Resets */
458482
.resets = r9a07g044_resets,
459483
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */

‎drivers/clk/renesas/r9a09g011-cpg.c

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,11 +23,14 @@
2323

2424
#define DIV_A DDIV_PACK(0x200, 0, 3)
2525
#define DIV_B DDIV_PACK(0x204, 0, 2)
26+
#define DIV_D DDIV_PACK(0x204, 4, 2)
2627
#define DIV_E DDIV_PACK(0x204, 8, 1)
2728
#define DIV_W DDIV_PACK(0x328, 0, 3)
2829

2930
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
31+
#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
3032
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
33+
#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
3134
#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
3235

3336
enum clk_ids {
@@ -50,11 +53,14 @@ enum clk_ids {
5053
CLK_PLL4,
5154
CLK_DIV_A,
5255
CLK_DIV_B,
56+
CLK_DIV_D,
5357
CLK_DIV_E,
5458
CLK_DIV_W,
5559
CLK_SEL_B,
5660
CLK_SEL_B_D2,
61+
CLK_SEL_D,
5762
CLK_SEL_E,
63+
CLK_SEL_SDI,
5864
CLK_SEL_W0,
5965

6066
/* Module Clocks */
@@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = {
8187
{0, 0},
8288
};
8389

90+
static const struct clk_div_table dtable_divd[] = {
91+
{0, 1},
92+
{1, 2},
93+
{2, 4},
94+
{0, 0},
95+
};
96+
97+
8498
static const struct clk_div_table dtable_divw[] = {
8599
{0, 6},
86100
{1, 7},
@@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = {
94108

95109
/* Mux clock tables */
96110
static const char * const sel_b[] = { ".main", ".divb" };
111+
static const char * const sel_d[] = { ".main", ".divd" };
97112
static const char * const sel_e[] = { ".main", ".dive" };
98113
static const char * const sel_w[] = { ".main", ".divw" };
114+
static const char * const sel_sdi[] = { ".main", ".pll2_200" };
99115

100116
static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
101117
/* External Clock Inputs */
@@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
115131

116132
DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
117133
DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
134+
DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd),
118135
DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
119136
DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
120137

121138
DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
139+
DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
122140
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
141+
DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
123142
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
124143

125144
DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
@@ -128,30 +147,84 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
128147
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
129148
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
130149
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
150+
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
151+
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
152+
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
153+
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
154+
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
155+
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
156+
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
157+
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
158+
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
159+
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
160+
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
161+
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
131162
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
132163
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
133164
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
165+
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
166+
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
167+
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
134168
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
135169
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
170+
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
171+
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4),
172+
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5),
173+
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6),
174+
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7),
175+
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8),
176+
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9),
177+
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10),
178+
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11),
136179
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
180+
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0),
181+
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4),
182+
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5),
183+
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6),
184+
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7),
185+
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8),
186+
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9),
187+
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10),
188+
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11),
137189
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
138190
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
191+
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0),
192+
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
193+
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
194+
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
195+
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
196+
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
197+
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
198+
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
139199
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
140200
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
141201
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
142202
};
143203

144204
static const struct rzg2l_reset r9a09g011_resets[] = {
145205
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
206+
DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6),
207+
DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7),
208+
DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8),
209+
DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7),
210+
DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8),
211+
DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9),
212+
DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10),
146213
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
147214
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
215+
DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
216+
DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
217+
DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
148218
DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
149219
DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
150220
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
151221
};
152222

153223
static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
154224
MOD_CLK_BASE + R9A09G011_CA53_CLK,
225+
MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,
226+
MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,
227+
MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
155228
MOD_CLK_BASE + R9A09G011_GIC_CLK,
156229
MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
157230
MOD_CLK_BASE + R9A09G011_URT_PCLK,

‎drivers/clk/renesas/rcar-gen4-cpg.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ enum rcar_gen4_clk_types {
1515
CLK_TYPE_GEN4_PLL2,
1616
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
1717
CLK_TYPE_GEN4_PLL3,
18-
CLK_TYPE_GEN4_PLL5,
1918
CLK_TYPE_GEN4_PLL4,
19+
CLK_TYPE_GEN4_PLL5,
2020
CLK_TYPE_GEN4_PLL6,
2121
CLK_TYPE_GEN4_SDSRC,
2222
CLK_TYPE_GEN4_SDH,

‎drivers/clk/renesas/renesas-cpg-mssr.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -989,7 +989,6 @@ static int __init cpg_mssr_common_init(struct device *dev,
989989
goto out_err;
990990
}
991991

992-
cpg_mssr_priv = priv;
993992
priv->num_core_clks = info->num_total_core_clks;
994993
priv->num_mod_clks = info->num_hw_mod_clks;
995994
priv->last_dt_core_clk = info->last_dt_core_clk;
@@ -1019,6 +1018,8 @@ static int __init cpg_mssr_common_init(struct device *dev,
10191018
if (error)
10201019
goto out_err;
10211020

1021+
cpg_mssr_priv = priv;
1022+
10221023
return 0;
10231024

10241025
out_err:

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