Skip to content

Commit cf04212

Browse files
Rubuschjic23
authored andcommitted
iio: accel: adxl345: add FIFO with watermark events
Add a basic setup for FIFO with configurable watermark. Add a handler for watermark interrupt events and extend the channel for the scan_index needed for the iio channel. The sensor is configurable to use a FIFO_BYPASSED mode or a FIFO_STREAM mode. For the FIFO_STREAM mode now a watermark can be configured, or disabled by setting 0. Further features require a working FIFO setup. Signed-off-by: Lothar Rubusch <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jonathan Cameron <[email protected]>
1 parent af38b0f commit cf04212

File tree

2 files changed

+323
-11
lines changed

2 files changed

+323
-11
lines changed

drivers/iio/accel/adxl345.h

Lines changed: 20 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,18 +15,31 @@
1515
#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
1616
#define ADXL345_REG_BW_RATE 0x2C
1717
#define ADXL345_REG_POWER_CTL 0x2D
18+
#define ADXL345_REG_INT_ENABLE 0x2E
19+
#define ADXL345_REG_INT_MAP 0x2F
20+
#define ADXL345_REG_INT_SOURCE 0x30
21+
#define ADXL345_REG_INT_SOURCE_MSK 0xFF
1822
#define ADXL345_REG_DATA_FORMAT 0x31
19-
#define ADXL345_REG_DATAX0 0x32
20-
#define ADXL345_REG_DATAY0 0x34
21-
#define ADXL345_REG_DATAZ0 0x36
22-
#define ADXL345_REG_DATA_AXIS(index) \
23-
(ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
23+
#define ADXL345_REG_XYZ_BASE 0x32
24+
#define ADXL345_REG_DATA_AXIS(index) \
25+
(ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16))
2426

27+
#define ADXL345_REG_FIFO_CTL 0x38
28+
#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0)
29+
/* 0: INT1, 1: INT2 */
30+
#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5)
31+
#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6)
32+
#define ADXL345_REG_FIFO_STATUS 0x39
33+
#define ADXL345_REG_FIFO_STATUS_MSK 0x3F
34+
35+
#define ADXL345_INT_OVERRUN BIT(0)
36+
#define ADXL345_INT_WATERMARK BIT(1)
37+
#define ADXL345_INT_DATA_READY BIT(7)
2538
#define ADXL345_BW_RATE GENMASK(3, 0)
2639
#define ADXL345_BASE_RATE_NANO_HZ 97656250LL
2740

28-
#define ADXL345_POWER_CTL_MEASURE BIT(3)
2941
#define ADXL345_POWER_CTL_STANDBY 0x00
42+
#define ADXL345_POWER_CTL_MEASURE BIT(3)
3043

3144
#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */
3245
#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */
@@ -40,6 +53,7 @@
4053
#define ADXL345_DATA_FORMAT_16G 3
4154

4255
#define ADXL345_DEVID 0xE5
56+
#define ADXL345_FIFO_SIZE 32
4357

4458
/*
4559
* In full-resolution mode, scale factor is maintained at ~4 mg/LSB

0 commit comments

Comments
 (0)