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15 | 15 | #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
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16 | 16 | #define ADXL345_REG_BW_RATE 0x2C
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17 | 17 | #define ADXL345_REG_POWER_CTL 0x2D
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| 18 | +#define ADXL345_REG_INT_ENABLE 0x2E |
| 19 | +#define ADXL345_REG_INT_MAP 0x2F |
| 20 | +#define ADXL345_REG_INT_SOURCE 0x30 |
| 21 | +#define ADXL345_REG_INT_SOURCE_MSK 0xFF |
18 | 22 | #define ADXL345_REG_DATA_FORMAT 0x31
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19 |
| -#define ADXL345_REG_DATAX0 0x32 |
20 |
| -#define ADXL345_REG_DATAY0 0x34 |
21 |
| -#define ADXL345_REG_DATAZ0 0x36 |
22 |
| -#define ADXL345_REG_DATA_AXIS(index) \ |
23 |
| - (ADXL345_REG_DATAX0 + (index) * sizeof(__le16)) |
| 23 | +#define ADXL345_REG_XYZ_BASE 0x32 |
| 24 | +#define ADXL345_REG_DATA_AXIS(index) \ |
| 25 | + (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) |
24 | 26 |
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| 27 | +#define ADXL345_REG_FIFO_CTL 0x38 |
| 28 | +#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) |
| 29 | +/* 0: INT1, 1: INT2 */ |
| 30 | +#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) |
| 31 | +#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) |
| 32 | +#define ADXL345_REG_FIFO_STATUS 0x39 |
| 33 | +#define ADXL345_REG_FIFO_STATUS_MSK 0x3F |
| 34 | + |
| 35 | +#define ADXL345_INT_OVERRUN BIT(0) |
| 36 | +#define ADXL345_INT_WATERMARK BIT(1) |
| 37 | +#define ADXL345_INT_DATA_READY BIT(7) |
25 | 38 | #define ADXL345_BW_RATE GENMASK(3, 0)
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26 | 39 | #define ADXL345_BASE_RATE_NANO_HZ 97656250LL
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27 | 40 |
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28 |
| -#define ADXL345_POWER_CTL_MEASURE BIT(3) |
29 | 41 | #define ADXL345_POWER_CTL_STANDBY 0x00
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| 42 | +#define ADXL345_POWER_CTL_MEASURE BIT(3) |
30 | 43 |
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31 | 44 | #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */
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32 | 45 | #define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */
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40 | 53 | #define ADXL345_DATA_FORMAT_16G 3
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41 | 54 |
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42 | 55 | #define ADXL345_DEVID 0xE5
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| 56 | +#define ADXL345_FIFO_SIZE 32 |
43 | 57 |
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44 | 58 | /*
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45 | 59 | * In full-resolution mode, scale factor is maintained at ~4 mg/LSB
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