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yghannam
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EDAC/amd64: Remove PCI Function 0
PCI Function 0 is used on Family 17h and later only to read the "dhar" value. This value is printed and provided through a module-specific debug sysfs file. The value is not used for any Family 17h and later code, and it does not have any apparent debug value on these systems. Remove "dhar", Function 0 PCI IDs, and all related code. Signed-off-by: Yazen Ghannam <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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-43
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2 files changed

+7
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‎drivers/edac/amd64_edac.c

Lines changed: 5 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1428,9 +1428,6 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
14281428

14291429
debug_display_dimm_sizes_df(pvt, i);
14301430
}
1431-
1432-
edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
1433-
pvt->dhar, dhar_base(pvt));
14341431
}
14351432

14361433
/* Display and decode various NB registers for debug purposes. */
@@ -1465,6 +1462,8 @@ static void __dump_misc_regs(struct amd64_pvt *pvt)
14651462
/* Only if NOT ganged does dclr1 have valid info */
14661463
if (!dct_ganging_enabled(pvt))
14671464
debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
1465+
1466+
edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
14681467
}
14691468

14701469
/* Display and decode various NB registers for debug purposes. */
@@ -1475,8 +1474,6 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
14751474
else
14761475
__dump_misc_regs(pvt);
14771476

1478-
edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
1479-
14801477
amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
14811478
}
14821479

@@ -2905,7 +2902,6 @@ static struct amd64_family_type family_types[] = {
29052902
},
29062903
[F17_CPUS] = {
29072904
.ctl_name = "F17h",
2908-
.f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
29092905
.max_mcs = 2,
29102906
.ops = {
29112907
.early_channel_count = f17_early_channel_count,
@@ -2914,7 +2910,6 @@ static struct amd64_family_type family_types[] = {
29142910
},
29152911
[F17_M10H_CPUS] = {
29162912
.ctl_name = "F17h_M10h",
2917-
.f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
29182913
.max_mcs = 2,
29192914
.ops = {
29202915
.early_channel_count = f17_early_channel_count,
@@ -2923,7 +2918,6 @@ static struct amd64_family_type family_types[] = {
29232918
},
29242919
[F17_M30H_CPUS] = {
29252920
.ctl_name = "F17h_M30h",
2926-
.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
29272921
.max_mcs = 8,
29282922
.ops = {
29292923
.early_channel_count = f17_early_channel_count,
@@ -2932,7 +2926,6 @@ static struct amd64_family_type family_types[] = {
29322926
},
29332927
[F17_M60H_CPUS] = {
29342928
.ctl_name = "F17h_M60h",
2935-
.f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,
29362929
.max_mcs = 2,
29372930
.ops = {
29382931
.early_channel_count = f17_early_channel_count,
@@ -2941,7 +2934,6 @@ static struct amd64_family_type family_types[] = {
29412934
},
29422935
[F17_M70H_CPUS] = {
29432936
.ctl_name = "F17h_M70h",
2944-
.f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,
29452937
.max_mcs = 2,
29462938
.ops = {
29472939
.early_channel_count = f17_early_channel_count,
@@ -2950,7 +2942,6 @@ static struct amd64_family_type family_types[] = {
29502942
},
29512943
[F19_CPUS] = {
29522944
.ctl_name = "F19h",
2953-
.f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
29542945
.max_mcs = 8,
29552946
.ops = {
29562947
.early_channel_count = f17_early_channel_count,
@@ -2959,7 +2950,6 @@ static struct amd64_family_type family_types[] = {
29592950
},
29602951
[F19_M10H_CPUS] = {
29612952
.ctl_name = "F19h_M10h",
2962-
.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,
29632953
.max_mcs = 12,
29642954
.flags.zn_regs_v2 = 1,
29652955
.ops = {
@@ -2969,7 +2959,6 @@ static struct amd64_family_type family_types[] = {
29692959
},
29702960
[F19_M50H_CPUS] = {
29712961
.ctl_name = "F19h_M50h",
2972-
.f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
29732962
.max_mcs = 2,
29742963
.ops = {
29752964
.early_channel_count = f17_early_channel_count,
@@ -3282,26 +3271,12 @@ static void decode_umc_error(int node_id, struct mce *m)
32823271
/*
32833272
* Use pvt->F3 which contains the F3 CPU PCI device to get the related
32843273
* F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
3285-
* Reserve F0 on systems with a UMC.
32863274
*/
32873275
static int
32883276
reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
32893277
{
3290-
if (pvt->umc) {
3291-
pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
3292-
if (!pvt->F0) {
3293-
edac_dbg(1, "F0 not found, device 0x%x\n", pci_id1);
3294-
return -ENODEV;
3295-
}
3296-
3297-
if (!pci_ctl_dev)
3298-
pci_ctl_dev = &pvt->F0->dev;
3299-
3300-
edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
3301-
edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
3302-
3278+
if (pvt->umc)
33033279
return 0;
3304-
}
33053280

33063281
/* Reserve the ADDRESS MAP Device */
33073282
pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
@@ -3333,7 +3308,7 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
33333308
static void free_mc_sibling_devs(struct amd64_pvt *pvt)
33343309
{
33353310
if (pvt->umc) {
3336-
pci_dev_put(pvt->F0);
3311+
return;
33373312
} else {
33383313
pci_dev_put(pvt->F1);
33393314
pci_dev_put(pvt->F2);
@@ -3423,7 +3398,6 @@ static void read_mc_regs(struct amd64_pvt *pvt)
34233398

34243399
if (pvt->umc) {
34253400
__read_mc_regs_df(pvt);
3426-
amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);
34273401

34283402
goto skip;
34293403
}
@@ -4057,8 +4031,6 @@ static int hw_info_get(struct amd64_pvt *pvt)
40574031
pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
40584032
if (!pvt->umc)
40594033
return -ENOMEM;
4060-
4061-
pci_id1 = fam_type->f0_id;
40624034
} else {
40634035
pci_id1 = fam_type->f1_id;
40644036
pci_id2 = fam_type->f2_id;
@@ -4075,7 +4047,7 @@ static int hw_info_get(struct amd64_pvt *pvt)
40754047

40764048
static void hw_info_put(struct amd64_pvt *pvt)
40774049
{
4078-
if (pvt->F0 || pvt->F1)
4050+
if (pvt->F1)
40794051
free_mc_sibling_devs(pvt);
40804052

40814053
kfree(pvt->umc);

‎drivers/edac/amd64_edac.h

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -114,14 +114,6 @@
114114
#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
115115
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
116116
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
117-
#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
118-
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
119-
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
120-
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
121-
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
122-
#define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
123-
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
124-
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
125117

126118
/*
127119
* Function 1 - Address Map
@@ -346,7 +338,7 @@ struct amd64_pvt {
346338
struct low_ops *ops;
347339

348340
/* pci_device handles which we utilize */
349-
struct pci_dev *F0, *F1, *F2, *F3;
341+
struct pci_dev *F1, *F2, *F3;
350342

351343
u16 mc_node_id; /* MC index of this MC node */
352344
u8 fam; /* CPU family */
@@ -493,7 +485,7 @@ struct amd64_family_flags {
493485

494486
struct amd64_family_type {
495487
const char *ctl_name;
496-
u16 f0_id, f1_id, f2_id;
488+
u16 f1_id, f2_id;
497489
/* Maximum number of memory controllers per die/node. */
498490
u8 max_mcs;
499491
struct amd64_family_flags flags;

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