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Amit Kumar Mahapatraambarus
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dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register
If the WP# signal of the flash device is either not connected or is wrongly tied to GND (that includes internal pull-downs), and the software sets the status register write disable (SRWD) bit in the status register then the status register permanently becomes read-only. To avoid this added a new boolean DT property "no-wp". If this property is set in the DT then the software avoids setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Tudor Ambarus <[email protected]>
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Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

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@@ -70,6 +70,21 @@ properties:
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be used on such systems, to denote the absence of a reliable reset
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mechanism.
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no-wp:
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type: boolean
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description:
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The status register write disable (SRWD) bit in status register, combined
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with the WP# signal, provides hardware data protection for the device. When
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the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
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strapped to LOW, the status register nonvolatile bits become read-only and
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the WRITE STATUS REGISTER operation will not execute. The only way to exit
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this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
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flash device is not connected or is wrongly tied to GND (that includes internal
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pull-downs) then status register permanently becomes read-only as the SRWD bit
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cannot be reset. This boolean flag can be used on such systems to avoid setting
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the SRWD bit while writing the status register. WP# signal hard strapped to GND
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can be a valid use case.
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reset-gpios:
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description:
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A GPIO line connected to the RESET (active low) signal of the device.

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