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33 | 33 | #include <dt-bindings/power/rk3368-power.h>
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34 | 34 | #include <dt-bindings/power/rk3399-power.h>
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35 | 35 | #include <dt-bindings/power/rk3568-power.h>
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| 36 | +#include <dt-bindings/power/rockchip,rk3576-power.h> |
36 | 37 | #include <dt-bindings/power/rk3588-power.h>
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37 | 38 |
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38 | 39 | struct rockchip_domain_info {
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@@ -175,6 +176,9 @@ struct rockchip_pmu {
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175 | 176 | #define DOMAIN_RK3568(name, pwr, req, wakeup) \
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176 | 177 | DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
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177 | 178 |
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| 179 | +#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ |
| 180 | + DOMAIN_M_O_R(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, wakeup) |
| 181 | + |
178 | 182 | /*
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179 | 183 | * Dynamic Memory Controller may need to coordinate with us -- see
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180 | 184 | * rockchip_pmu_block().
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@@ -1106,6 +1110,28 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
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1106 | 1110 | [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
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1107 | 1111 | };
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1108 | 1112 |
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| 1113 | +static const struct rockchip_domain_info rk3576_pm_domains[] = { |
| 1114 | + [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, false), |
| 1115 | + [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), false), |
| 1116 | + [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), false), |
| 1117 | + [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), false), |
| 1118 | + [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), false), |
| 1119 | + [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, false), |
| 1120 | + [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, false), |
| 1121 | + [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), false), |
| 1122 | + [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), false), |
| 1123 | + [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), true), |
| 1124 | + [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), false), |
| 1125 | + [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), false), |
| 1126 | + [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), false), |
| 1127 | + [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), false), |
| 1128 | + [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), false), |
| 1129 | + [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, false), |
| 1130 | + [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), false), |
| 1131 | + [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), false), |
| 1132 | + [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), false), |
| 1133 | +}; |
| 1134 | + |
1109 | 1135 | static const struct rockchip_domain_info rk3588_pm_domains[] = {
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1110 | 1136 | [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
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1111 | 1137 | [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
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@@ -1284,6 +1310,21 @@ static const struct rockchip_pmu_info rk3568_pmu = {
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1284 | 1310 | .domain_info = rk3568_pm_domains,
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1285 | 1311 | };
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1286 | 1312 |
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| 1313 | +static const struct rockchip_pmu_info rk3576_pmu = { |
| 1314 | + .pwr_offset = 0x210, |
| 1315 | + .status_offset = 0x230, |
| 1316 | + .chain_status_offset = 0x248, |
| 1317 | + .mem_status_offset = 0x250, |
| 1318 | + .mem_pwr_offset = 0x300, |
| 1319 | + .req_offset = 0x110, |
| 1320 | + .idle_offset = 0x128, |
| 1321 | + .ack_offset = 0x120, |
| 1322 | + .repair_status_offset = 0x570, |
| 1323 | + |
| 1324 | + .num_domains = ARRAY_SIZE(rk3576_pm_domains), |
| 1325 | + .domain_info = rk3576_pm_domains, |
| 1326 | +}; |
| 1327 | + |
1287 | 1328 | static const struct rockchip_pmu_info rk3588_pmu = {
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1288 | 1329 | .pwr_offset = 0x14c,
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1289 | 1330 | .status_offset = 0x180,
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@@ -1359,6 +1400,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
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1359 | 1400 | .compatible = "rockchip,rk3568-power-controller",
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1360 | 1401 | .data = (void *)&rk3568_pmu,
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1361 | 1402 | },
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| 1403 | + { |
| 1404 | + .compatible = "rockchip,rk3576-power-controller", |
| 1405 | + .data = (void *)&rk3576_pmu, |
| 1406 | + }, |
1362 | 1407 | {
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1363 | 1408 | .compatible = "rockchip,rk3588-power-controller",
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1364 | 1409 | .data = (void *)&rk3588_pmu,
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