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iommu/arm-smmu: Add CB prefix to register bitfields
For consistency, add the "CB" prefix to the bitfield defines for context registers. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Pranjal Shrivastava <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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+41
-41
lines changed

5 files changed

+41
-41
lines changed

‎drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
200200
void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
201201

202202
fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
203-
if (!(fsr & ARM_SMMU_FSR_FAULT))
203+
if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
204204
return IRQ_NONE;
205205

206206
fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);

‎drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ static int qcom_tbu_halt(struct qcom_tbu *tbu, struct arm_smmu_domain *smmu_doma
141141
writel_relaxed(val, tbu->base + DEBUG_SID_HALT_REG);
142142

143143
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
144-
if ((fsr & ARM_SMMU_FSR_FAULT) && (fsr & ARM_SMMU_FSR_SS)) {
144+
if ((fsr & ARM_SMMU_CB_FSR_FAULT) && (fsr & ARM_SMMU_CB_FSR_SS)) {
145145
u32 sctlr_orig, sctlr;
146146

147147
/*
@@ -298,15 +298,15 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
298298
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
299299

300300
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
301-
if (fsr & ARM_SMMU_FSR_FAULT) {
301+
if (fsr & ARM_SMMU_CB_FSR_FAULT) {
302302
/* Clear pending interrupts */
303303
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
304304

305305
/*
306306
* TBU halt takes care of resuming any stalled transcation.
307307
* Kept it here for completeness sake.
308308
*/
309-
if (fsr & ARM_SMMU_FSR_SS)
309+
if (fsr & ARM_SMMU_CB_FSR_SS)
310310
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
311311
ARM_SMMU_RESUME_TERMINATE);
312312
}
@@ -320,11 +320,11 @@ static phys_addr_t qcom_iova_to_phys(struct arm_smmu_domain *smmu_domain,
320320
phys = qcom_tbu_trigger_atos(smmu_domain, tbu, iova, sid);
321321

322322
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
323-
if (fsr & ARM_SMMU_FSR_FAULT) {
323+
if (fsr & ARM_SMMU_CB_FSR_FAULT) {
324324
/* Clear pending interrupts */
325325
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
326326

327-
if (fsr & ARM_SMMU_FSR_SS)
327+
if (fsr & ARM_SMMU_CB_FSR_SS)
328328
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME,
329329
ARM_SMMU_RESUME_TERMINATE);
330330
}
@@ -394,7 +394,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
394394
DEFAULT_RATELIMIT_BURST);
395395

396396
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
397-
if (!(fsr & ARM_SMMU_FSR_FAULT))
397+
if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
398398
return IRQ_NONE;
399399

400400
fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
@@ -403,7 +403,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
403403

404404
if (list_empty(&tbu_list)) {
405405
ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
406-
fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
406+
fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
407407

408408
if (ret == -ENOSYS)
409409
dev_err_ratelimited(smmu->dev,
@@ -417,7 +417,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
417417
phys_soft = ops->iova_to_phys(ops, iova);
418418

419419
tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,
420-
fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
420+
fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
421421
if (!tmp || tmp == -EBUSY) {
422422
dev_dbg(smmu->dev,
423423
"Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n",
@@ -481,7 +481,7 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev)
481481
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
482482

483483
/* Retry or terminate any stalled transactions */
484-
if (fsr & ARM_SMMU_FSR_SS)
484+
if (fsr & ARM_SMMU_CB_FSR_SS)
485485
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);
486486
}
487487

‎drivers/iommu/arm/arm-smmu/arm-smmu.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -415,15 +415,15 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
415415
int ret;
416416

417417
fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
418-
if (!(fsr & ARM_SMMU_FSR_FAULT))
418+
if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
419419
return IRQ_NONE;
420420

421421
fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);
422422
iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
423423
cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
424424

425425
ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,
426-
fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
426+
fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
427427

428428
if (ret == -ENOSYS)
429429
dev_err_ratelimited(smmu->dev,
@@ -1306,7 +1306,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
13061306
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va);
13071307

13081308
reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR;
1309-
if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_ATSR_ACTIVE),
1309+
if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ARM_SMMU_CB_ATSR_ACTIVE),
13101310
5, 50)) {
13111311
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
13121312
dev_err(dev,
@@ -1642,7 +1642,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
16421642
/* Make sure all context banks are disabled and clear CB_FSR */
16431643
for (i = 0; i < smmu->num_context_banks; ++i) {
16441644
arm_smmu_write_context_bank(smmu, i);
1645-
arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
1645+
arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
16461646
}
16471647

16481648
/* Invalidate the TLB, just in case */

‎drivers/iommu/arm/arm-smmu/arm-smmu.h

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -196,34 +196,34 @@ enum arm_smmu_cbar_type {
196196
#define ARM_SMMU_CB_PAR_F BIT(0)
197197

198198
#define ARM_SMMU_CB_FSR 0x58
199-
#define ARM_SMMU_FSR_MULTI BIT(31)
200-
#define ARM_SMMU_FSR_SS BIT(30)
201-
#define ARM_SMMU_FSR_UUT BIT(8)
202-
#define ARM_SMMU_FSR_ASF BIT(7)
203-
#define ARM_SMMU_FSR_TLBLKF BIT(6)
204-
#define ARM_SMMU_FSR_TLBMCF BIT(5)
205-
#define ARM_SMMU_FSR_EF BIT(4)
206-
#define ARM_SMMU_FSR_PF BIT(3)
207-
#define ARM_SMMU_FSR_AFF BIT(2)
208-
#define ARM_SMMU_FSR_TF BIT(1)
209-
210-
#define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \
211-
ARM_SMMU_FSR_ASF | \
212-
ARM_SMMU_FSR_TLBMCF | \
213-
ARM_SMMU_FSR_TLBLKF)
214-
215-
#define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \
216-
ARM_SMMU_FSR_SS | \
217-
ARM_SMMU_FSR_UUT | \
218-
ARM_SMMU_FSR_EF | \
219-
ARM_SMMU_FSR_PF | \
220-
ARM_SMMU_FSR_TF | \
221-
ARM_SMMU_FSR_IGN)
199+
#define ARM_SMMU_CB_FSR_MULTI BIT(31)
200+
#define ARM_SMMU_CB_FSR_SS BIT(30)
201+
#define ARM_SMMU_CB_FSR_UUT BIT(8)
202+
#define ARM_SMMU_CB_FSR_ASF BIT(7)
203+
#define ARM_SMMU_CB_FSR_TLBLKF BIT(6)
204+
#define ARM_SMMU_CB_FSR_TLBMCF BIT(5)
205+
#define ARM_SMMU_CB_FSR_EF BIT(4)
206+
#define ARM_SMMU_CB_FSR_PF BIT(3)
207+
#define ARM_SMMU_CB_FSR_AFF BIT(2)
208+
#define ARM_SMMU_CB_FSR_TF BIT(1)
209+
210+
#define ARM_SMMU_CB_FSR_IGN (ARM_SMMU_CB_FSR_AFF | \
211+
ARM_SMMU_CB_FSR_ASF | \
212+
ARM_SMMU_CB_FSR_TLBMCF | \
213+
ARM_SMMU_CB_FSR_TLBLKF)
214+
215+
#define ARM_SMMU_CB_FSR_FAULT (ARM_SMMU_CB_FSR_MULTI | \
216+
ARM_SMMU_CB_FSR_SS | \
217+
ARM_SMMU_CB_FSR_UUT | \
218+
ARM_SMMU_CB_FSR_EF | \
219+
ARM_SMMU_CB_FSR_PF | \
220+
ARM_SMMU_CB_FSR_TF | \
221+
ARM_SMMU_CB_FSR_IGN)
222222

223223
#define ARM_SMMU_CB_FAR 0x60
224224

225225
#define ARM_SMMU_CB_FSYNR0 0x68
226-
#define ARM_SMMU_FSYNR0_WNR BIT(4)
226+
#define ARM_SMMU_CB_FSYNR0_WNR BIT(4)
227227

228228
#define ARM_SMMU_CB_FSYNR1 0x6c
229229

@@ -237,7 +237,7 @@ enum arm_smmu_cbar_type {
237237
#define ARM_SMMU_CB_ATS1PR 0x800
238238

239239
#define ARM_SMMU_CB_ATSR 0x8f0
240-
#define ARM_SMMU_ATSR_ACTIVE BIT(0)
240+
#define ARM_SMMU_CB_ATSR_ACTIVE BIT(0)
241241

242242
#define ARM_SMMU_RESUME_TERMINATE BIT(0)
243243

‎drivers/iommu/arm/arm-smmu/qcom_iommu.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
194194

195195
fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
196196

197-
if (!(fsr & ARM_SMMU_FSR_FAULT))
197+
if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
198198
return IRQ_NONE;
199199

200200
fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
@@ -274,7 +274,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
274274

275275
/* Clear context bank fault address fault status registers */
276276
iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
277-
iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
277+
iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
278278

279279
/* TTBRs */
280280
iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,

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