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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/controller/xilinx-xdma'
- Move Xilinx IRQ definitions to a common header shared by pcie-xilinx-cpm and xilinx-xdma (Thippeswamy Havalige) - Add Xilinx XDMA driver and DT schema (Thippeswamy Havalige) * pci/controller/xilinx-xdma: PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge PCI: xilinx-cpm: Move IRQ definitions to a common header
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‎Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx XDMA PL PCIe Root Port Bridge
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maintainers:
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- Thippeswamy Havalige <[email protected]>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: xlnx,xdma-host-3.00
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reg:
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maxItems: 1
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ranges:
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maxItems: 2
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interrupts:
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items:
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- description: interrupt asserted when miscellaneous interrupt is received.
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- description: msi0 interrupt asserted when an MSI is received.
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- description: msi1 interrupt asserted when an MSI is received.
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interrupt-names:
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items:
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- const: misc
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- const: msi0
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- const: msi1
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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interrupt-map:
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maxItems: 4
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"#interrupt-cells":
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const: 1
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interrupt-controller:
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description: identifies the node as an interrupt controller
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type: object
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properties:
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interrupt-controller: true
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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required:
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- interrupt-controller
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- "#address-cells"
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- "#interrupt-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- ranges
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- interrupts
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- interrupt-map
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- interrupt-map-mask
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- "#interrupt-cells"
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@a0000000 {
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compatible = "xlnx,xdma-host-3.00";
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reg = <0x0 0xa0000000 0x0 0x10000000>;
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ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
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<0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "misc", "msi0", "msi1";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
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<0 0 0 2 &pcie_intc_0 1>,
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<0 0 0 3 &pcie_intc_0 2>,
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<0 0 0 4 &pcie_intc_0 3>;
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};

‎drivers/pci/controller/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -324,6 +324,17 @@ config PCIE_XILINX
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Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
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Host Bridge driver.
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config PCIE_XILINX_DMA_PL
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bool "Xilinx DMA PL PCIe host bridge support"
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depends on ARCH_ZYNQMP || COMPILE_TEST
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depends on PCI_MSI
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select PCI_HOST_COMMON
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help
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Say 'Y' here if you want kernel support for the Xilinx PL DMA
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PCIe host bridge. The controller is a Soft IP which can act as
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Root Port. If your system provides Xilinx PCIe host controller
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bridge DMA as Soft IP say 'Y'; if you are not sure, say 'N'.
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config PCIE_XILINX_NWL
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bool "Xilinx NWL PCIe controller"
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depends on ARCH_ZYNQMP || COMPILE_TEST

‎drivers/pci/controller/Makefile

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@@ -17,6 +17,7 @@ obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
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obj-$(CONFIG_PCIE_XILINX_CPM) += pcie-xilinx-cpm.o
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obj-$(CONFIG_PCIE_XILINX_DMA_PL) += pcie-xilinx-dma-pl.o
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obj-$(CONFIG_PCI_V3_SEMI) += pci-v3-semi.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o

‎drivers/pci/controller/pcie-xilinx-common.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2023, Xilinx, Inc.
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*/
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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/* Interrupt registers definitions */
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#define XILINX_PCIE_INTR_LINK_DOWN 0
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#define XILINX_PCIE_INTR_HOT_RESET 3
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#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT 4
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#define XILINX_PCIE_INTR_CFG_TIMEOUT 8
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#define XILINX_PCIE_INTR_CORRECTABLE 9
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#define XILINX_PCIE_INTR_NONFATAL 10
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#define XILINX_PCIE_INTR_FATAL 11
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#define XILINX_PCIE_INTR_CFG_ERR_POISON 12
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#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD 15
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#define XILINX_PCIE_INTR_INTX 16
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#define XILINX_PCIE_INTR_PM_PME_RCVD 17
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#define XILINX_PCIE_INTR_MSI 17
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#define XILINX_PCIE_INTR_SLV_UNSUPP 20
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#define XILINX_PCIE_INTR_SLV_UNEXP 21
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#define XILINX_PCIE_INTR_SLV_COMPL 22
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#define XILINX_PCIE_INTR_SLV_ERRP 23
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#define XILINX_PCIE_INTR_SLV_CMPABT 24
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#define XILINX_PCIE_INTR_SLV_ILLBUR 25
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#define XILINX_PCIE_INTR_MST_DECERR 26
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#define XILINX_PCIE_INTR_MST_SLVERR 27
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#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT 28

‎drivers/pci/controller/pcie-xilinx-cpm.c

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@@ -16,11 +16,9 @@
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
1818
#include <linux/of_platform.h>
19-
#include <linux/pci.h>
20-
#include <linux/platform_device.h>
21-
#include <linux/pci-ecam.h>
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2320
#include "../pci.h"
21+
#include "pcie-xilinx-common.h"
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2523
/* Register definitions */
2624
#define XILINX_CPM_PCIE_REG_IDR 0x00000E10
@@ -38,29 +36,7 @@
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#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
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#define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
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/* Interrupt registers definitions */
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#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
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#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
44-
#define XILINX_CPM_PCIE_INTR_CFG_PCIE_TIMEOUT 4
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#define XILINX_CPM_PCIE_INTR_CFG_TIMEOUT 8
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#define XILINX_CPM_PCIE_INTR_CORRECTABLE 9
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#define XILINX_CPM_PCIE_INTR_NONFATAL 10
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#define XILINX_CPM_PCIE_INTR_FATAL 11
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#define XILINX_CPM_PCIE_INTR_CFG_ERR_POISON 12
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#define XILINX_CPM_PCIE_INTR_PME_TO_ACK_RCVD 15
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#define XILINX_CPM_PCIE_INTR_INTX 16
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#define XILINX_CPM_PCIE_INTR_PM_PME_RCVD 17
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#define XILINX_CPM_PCIE_INTR_SLV_UNSUPP 20
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#define XILINX_CPM_PCIE_INTR_SLV_UNEXP 21
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#define XILINX_CPM_PCIE_INTR_SLV_COMPL 22
56-
#define XILINX_CPM_PCIE_INTR_SLV_ERRP 23
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#define XILINX_CPM_PCIE_INTR_SLV_CMPABT 24
58-
#define XILINX_CPM_PCIE_INTR_SLV_ILLBUR 25
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#define XILINX_CPM_PCIE_INTR_MST_DECERR 26
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#define XILINX_CPM_PCIE_INTR_MST_SLVERR 27
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#define XILINX_CPM_PCIE_INTR_SLV_PCIE_TIMEOUT 28
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63-
#define IMR(x) BIT(XILINX_CPM_PCIE_INTR_ ##x)
39+
#define IMR(x) BIT(XILINX_PCIE_INTR_ ##x)
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6541
#define XILINX_CPM_PCIE_IMR_ALL_MASK \
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( \
@@ -323,7 +299,7 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
323299
}
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325301
#define _IC(x, s) \
326-
[XILINX_CPM_PCIE_INTR_ ## x] = { __stringify(x), s }
302+
[XILINX_PCIE_INTR_ ## x] = { __stringify(x), s }
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328304
static const struct {
329305
const char *sym;
@@ -359,9 +335,9 @@ static irqreturn_t xilinx_cpm_pcie_intr_handler(int irq, void *dev_id)
359335
d = irq_domain_get_irq_data(port->cpm_domain, irq);
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361337
switch (d->hwirq) {
362-
case XILINX_CPM_PCIE_INTR_CORRECTABLE:
363-
case XILINX_CPM_PCIE_INTR_NONFATAL:
364-
case XILINX_CPM_PCIE_INTR_FATAL:
338+
case XILINX_PCIE_INTR_CORRECTABLE:
339+
case XILINX_PCIE_INTR_NONFATAL:
340+
case XILINX_PCIE_INTR_FATAL:
365341
cpm_pcie_clear_err_interrupts(port);
366342
fallthrough;
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@@ -466,7 +442,7 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port)
466442
}
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468444
port->intx_irq = irq_create_mapping(port->cpm_domain,
469-
XILINX_CPM_PCIE_INTR_INTX);
445+
XILINX_PCIE_INTR_INTX);
470446
if (!port->intx_irq) {
471447
dev_err(dev, "Failed to map INTx interrupt\n");
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return -ENXIO;

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