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Zhiqiang-HouLorenzo Pieralisi
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PCI: layerscape: Change to use the DWC common link-up check function
The current Layerscape PCIe driver directly uses the physical layer LTSSM code to check the link-up state, which treats the > L0 states as link-up. This is not correct, since there is not explicit map between link-up state and LTSSM. So this patch changes to use the DWC common link-up check function. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
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drivers/pci/controller/dwc/pci-layerscape.c

Lines changed: 11 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* PCIe host controller driver for Freescale Layerscape SoCs
44
*
55
* Copyright (C) 2014 Freescale Semiconductor.
6+
* Copyright 2021 NXP
67
*
78
* Author: Minghuan Lian <[email protected]>
89
*/
@@ -22,33 +23,15 @@
2223

2324
#include "pcie-designware.h"
2425

25-
/* PEX1/2 Misc Ports Status Register */
26-
#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
27-
#define LTSSM_STATE_SHIFT 20
28-
#define LTSSM_STATE_MASK 0x3f
29-
#define LTSSM_PCIE_L0 0x11 /* L0 state */
30-
3126
/* PEX Internal Configuration Registers */
3227
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
3328
#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
3429
#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
3530

3631
#define PCIE_IATU_NUM 6
3732

38-
struct ls_pcie_drvdata {
39-
u32 lut_offset;
40-
u32 ltssm_shift;
41-
u32 lut_dbg;
42-
const struct dw_pcie_host_ops *ops;
43-
const struct dw_pcie_ops *dw_pcie_ops;
44-
};
45-
4633
struct ls_pcie {
4734
struct dw_pcie *pci;
48-
void __iomem *lut;
49-
struct regmap *scfg;
50-
const struct ls_pcie_drvdata *drvdata;
51-
int index;
5235
};
5336

5437
#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
@@ -83,38 +66,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
8366
iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
8467
}
8568

86-
static int ls1021_pcie_link_up(struct dw_pcie *pci)
87-
{
88-
u32 state;
89-
struct ls_pcie *pcie = to_ls_pcie(pci);
90-
91-
if (!pcie->scfg)
92-
return 0;
93-
94-
regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
95-
state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
96-
97-
if (state < LTSSM_PCIE_L0)
98-
return 0;
99-
100-
return 1;
101-
}
102-
103-
static int ls_pcie_link_up(struct dw_pcie *pci)
104-
{
105-
struct ls_pcie *pcie = to_ls_pcie(pci);
106-
u32 state;
107-
108-
state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
109-
pcie->drvdata->ltssm_shift) &
110-
LTSSM_STATE_MASK;
111-
112-
if (state < LTSSM_PCIE_L0)
113-
return 0;
114-
115-
return 1;
116-
}
117-
11869
/* Forward error response of outbound non-posted requests */
11970
static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
12071
{
@@ -139,96 +90,20 @@ static int ls_pcie_host_init(struct pcie_port *pp)
13990
return 0;
14091
}
14192

142-
static int ls1021_pcie_host_init(struct pcie_port *pp)
143-
{
144-
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
145-
struct ls_pcie *pcie = to_ls_pcie(pci);
146-
struct device *dev = pci->dev;
147-
u32 index[2];
148-
int ret;
149-
150-
pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
151-
"fsl,pcie-scfg");
152-
if (IS_ERR(pcie->scfg)) {
153-
ret = PTR_ERR(pcie->scfg);
154-
dev_err(dev, "No syscfg phandle specified\n");
155-
pcie->scfg = NULL;
156-
return ret;
157-
}
158-
159-
if (of_property_read_u32_array(dev->of_node,
160-
"fsl,pcie-scfg", index, 2)) {
161-
pcie->scfg = NULL;
162-
return -EINVAL;
163-
}
164-
pcie->index = index[1];
165-
166-
return ls_pcie_host_init(pp);
167-
}
168-
169-
static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
170-
.host_init = ls1021_pcie_host_init,
171-
};
172-
17393
static const struct dw_pcie_host_ops ls_pcie_host_ops = {
17494
.host_init = ls_pcie_host_init,
17595
};
17696

177-
static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
178-
.link_up = ls1021_pcie_link_up,
179-
};
180-
181-
static const struct dw_pcie_ops dw_ls_pcie_ops = {
182-
.link_up = ls_pcie_link_up,
183-
};
184-
185-
static const struct ls_pcie_drvdata ls1021_drvdata = {
186-
.ops = &ls1021_pcie_host_ops,
187-
.dw_pcie_ops = &dw_ls1021_pcie_ops,
188-
};
189-
190-
static const struct ls_pcie_drvdata ls1043_drvdata = {
191-
.lut_offset = 0x10000,
192-
.ltssm_shift = 24,
193-
.lut_dbg = 0x7fc,
194-
.ops = &ls_pcie_host_ops,
195-
.dw_pcie_ops = &dw_ls_pcie_ops,
196-
};
197-
198-
static const struct ls_pcie_drvdata ls1046_drvdata = {
199-
.lut_offset = 0x80000,
200-
.ltssm_shift = 24,
201-
.lut_dbg = 0x407fc,
202-
.ops = &ls_pcie_host_ops,
203-
.dw_pcie_ops = &dw_ls_pcie_ops,
204-
};
205-
206-
static const struct ls_pcie_drvdata ls2080_drvdata = {
207-
.lut_offset = 0x80000,
208-
.ltssm_shift = 0,
209-
.lut_dbg = 0x7fc,
210-
.ops = &ls_pcie_host_ops,
211-
.dw_pcie_ops = &dw_ls_pcie_ops,
212-
};
213-
214-
static const struct ls_pcie_drvdata ls2088_drvdata = {
215-
.lut_offset = 0x80000,
216-
.ltssm_shift = 0,
217-
.lut_dbg = 0x407fc,
218-
.ops = &ls_pcie_host_ops,
219-
.dw_pcie_ops = &dw_ls_pcie_ops,
220-
};
221-
22297
static const struct of_device_id ls_pcie_of_match[] = {
223-
{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
224-
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
225-
{ .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },
226-
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
227-
{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
228-
{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
229-
{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
230-
{ .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
231-
{ .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
98+
{ .compatible = "fsl,ls1012a-pcie", },
99+
{ .compatible = "fsl,ls1021a-pcie", },
100+
{ .compatible = "fsl,ls1028a-pcie", },
101+
{ .compatible = "fsl,ls1043a-pcie", },
102+
{ .compatible = "fsl,ls1046a-pcie", },
103+
{ .compatible = "fsl,ls2080a-pcie", },
104+
{ .compatible = "fsl,ls2085a-pcie", },
105+
{ .compatible = "fsl,ls2088a-pcie", },
106+
{ .compatible = "fsl,ls1088a-pcie", },
232107
{ },
233108
};
234109

@@ -247,11 +122,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
247122
if (!pci)
248123
return -ENOMEM;
249124

250-
pcie->drvdata = of_device_get_match_data(dev);
251-
252125
pci->dev = dev;
253-
pci->ops = pcie->drvdata->dw_pcie_ops;
254-
pci->pp.ops = pcie->drvdata->ops;
126+
pci->pp.ops = &ls_pcie_host_ops;
255127

256128
pcie->pci = pci;
257129

@@ -260,8 +132,6 @@ static int ls_pcie_probe(struct platform_device *pdev)
260132
if (IS_ERR(pci->dbi_base))
261133
return PTR_ERR(pci->dbi_base);
262134

263-
pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
264-
265135
if (!ls_pcie_is_bridge(pcie))
266136
return -ENODEV;
267137

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