Skip to content

Commit d2a08e4

Browse files
Evan Quanalexdeucher
authored andcommitted
drm/amd/powerplay: correct fine grained dpm force level setting
For fine grained dpm, there is only two levels supported. However to reflect correctly the current clock frequency, there is an intermediate level faked. Thus on forcing level setting, we need to treat level 2 correctly as level 1. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent 355d991 commit d2a08e4

File tree

1 file changed

+6
-0
lines changed

1 file changed

+6
-0
lines changed

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -759,6 +759,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
759759
case SMU_UCLK:
760760
case SMU_DCEFCLK:
761761
case SMU_FCLK:
762+
/* There is only 2 levels for fine grained DPM */
763+
if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
764+
soft_max_level = (soft_max_level >= 1 ? 1 : 0);
765+
soft_min_level = (soft_min_level >= 1 ? 1 : 0);
766+
}
767+
762768
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
763769
if (ret)
764770
return size;

0 commit comments

Comments
 (0)