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#define ARM_CSPMU_ACTIVE_CPU_MASK 0x0
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#define ARM_CSPMU_ASSOCIATED_CPU_MASK 0x1
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- /* Check if field f in flags is set with value v */
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- #define CHECK_APMT_FLAG (flags , f , v ) \
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- ((flags & (ACPI_APMT_FLAGS_ ## f)) == (ACPI_APMT_FLAGS_ ## f ## _ ## v))
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-
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/* Check and use default if implementer doesn't provide attribute callback */
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#define CHECK_DEFAULT_IMPL_OPS (ops , callback ) \
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do { \
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static unsigned long arm_cspmu_cpuhp_state ;
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+ static struct acpi_apmt_node * arm_cspmu_apmt_node (struct device * dev )
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+ {
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+ return * (struct acpi_apmt_node * * )dev_get_platdata (dev );
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+ }
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+
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/*
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* In CoreSight PMU architecture, all of the MMIO registers are 32-bit except
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* counter register. The counter register can be implemented as 32-bit or 64-bit
@@ -155,12 +156,6 @@ static u64 read_reg64_hilohi(const void __iomem *addr, u32 max_poll_count)
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return val ;
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}
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- /* Check if PMU supports 64-bit single copy atomic. */
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- static inline bool supports_64bit_atomics (const struct arm_cspmu * cspmu )
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- {
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- return CHECK_APMT_FLAG (cspmu -> apmt_node -> flags , ATOMIC , SUPP );
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- }
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-
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/* Check if cycle counter is supported. */
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static inline bool supports_cycle_counter (const struct arm_cspmu * cspmu )
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{
@@ -319,7 +314,7 @@ static const char *arm_cspmu_get_name(const struct arm_cspmu *cspmu)
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static atomic_t pmu_idx [ACPI_APMT_NODE_TYPE_COUNT ] = { 0 };
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dev = cspmu -> dev ;
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- apmt_node = cspmu -> apmt_node ;
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+ apmt_node = arm_cspmu_apmt_node ( dev ) ;
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pmu_type = apmt_node -> type ;
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if (pmu_type >= ACPI_APMT_NODE_TYPE_COUNT ) {
@@ -396,8 +391,8 @@ static const struct impl_match impl_match[] = {
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static int arm_cspmu_init_impl_ops (struct arm_cspmu * cspmu )
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{
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int ret ;
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- struct acpi_apmt_node * apmt_node = cspmu -> apmt_node ;
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struct arm_cspmu_impl_ops * impl_ops = & cspmu -> impl .ops ;
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+ struct acpi_apmt_node * apmt_node = arm_cspmu_apmt_node (cspmu -> dev );
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const struct impl_match * match = impl_match ;
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/*
@@ -719,7 +714,7 @@ static u64 arm_cspmu_read_counter(struct perf_event *event)
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offset = counter_offset (sizeof (u64 ), event -> hw .idx );
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counter_addr = cspmu -> base1 + offset ;
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- return supports_64bit_atomics ( cspmu ) ?
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+ return cspmu -> has_atomic_dword ?
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readq (counter_addr ) :
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read_reg64_hilohi (counter_addr , HILOHI_MAX_POLL );
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}
@@ -910,36 +905,28 @@ static struct arm_cspmu *arm_cspmu_alloc(struct platform_device *pdev)
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{
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struct acpi_apmt_node * apmt_node ;
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struct arm_cspmu * cspmu ;
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- struct device * dev ;
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-
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- dev = & pdev -> dev ;
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- apmt_node = * (struct acpi_apmt_node * * )dev_get_platdata (dev );
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- if (!apmt_node ) {
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- dev_err (dev , "failed to get APMT node\n" );
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- return NULL ;
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- }
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+ struct device * dev = & pdev -> dev ;
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cspmu = devm_kzalloc (dev , sizeof (* cspmu ), GFP_KERNEL );
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if (!cspmu )
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return NULL ;
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cspmu -> dev = dev ;
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- cspmu -> apmt_node = apmt_node ;
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-
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platform_set_drvdata (pdev , cspmu );
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+ apmt_node = arm_cspmu_apmt_node (dev );
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+ cspmu -> has_atomic_dword = apmt_node -> flags & ACPI_APMT_FLAGS_ATOMIC ;
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+
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return cspmu ;
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}
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static int arm_cspmu_init_mmio (struct arm_cspmu * cspmu )
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{
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struct device * dev ;
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struct platform_device * pdev ;
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- struct acpi_apmt_node * apmt_node ;
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dev = cspmu -> dev ;
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pdev = to_platform_device (dev );
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- apmt_node = cspmu -> apmt_node ;
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/* Base address for page 0. */
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cspmu -> base0 = devm_platform_ioremap_resource (pdev , 0 );
@@ -950,7 +937,7 @@ static int arm_cspmu_init_mmio(struct arm_cspmu *cspmu)
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/* Base address for page 1 if supported. Otherwise point to page 0. */
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cspmu -> base1 = cspmu -> base0 ;
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- if (CHECK_APMT_FLAG ( apmt_node -> flags , DUAL_PAGE , SUPP )) {
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+ if (platform_get_resource ( pdev , IORESOURCE_MEM , 1 )) {
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cspmu -> base1 = devm_platform_ioremap_resource (pdev , 1 );
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if (IS_ERR (cspmu -> base1 )) {
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dev_err (dev , "ioremap failed for page-1 resource\n" );
@@ -1047,19 +1034,14 @@ static int arm_cspmu_request_irq(struct arm_cspmu *cspmu)
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int irq , ret ;
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struct device * dev ;
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struct platform_device * pdev ;
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- struct acpi_apmt_node * apmt_node ;
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dev = cspmu -> dev ;
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pdev = to_platform_device (dev );
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- apmt_node = cspmu -> apmt_node ;
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/* Skip IRQ request if the PMU does not support overflow interrupt. */
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- if (apmt_node -> ovflw_irq == 0 )
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- return 0 ;
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-
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- irq = platform_get_irq (pdev , 0 );
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+ irq = platform_get_irq_optional (pdev , 0 );
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if (irq < 0 )
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- return irq ;
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+ return irq == - ENXIO ? 0 : irq ;
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ret = devm_request_irq (dev , irq , arm_cspmu_handle_irq ,
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IRQF_NOBALANCING | IRQF_NO_THREAD , dev_name (dev ),
@@ -1103,13 +1085,11 @@ static inline int arm_cspmu_find_cpu_container(int cpu, u32 container_uid)
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static int arm_cspmu_acpi_get_cpus (struct arm_cspmu * cspmu )
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{
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- struct device * dev ;
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struct acpi_apmt_node * apmt_node ;
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int affinity_flag ;
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int cpu ;
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- dev = cspmu -> pmu .dev ;
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- apmt_node = cspmu -> apmt_node ;
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+ apmt_node = arm_cspmu_apmt_node (cspmu -> dev );
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affinity_flag = apmt_node -> flags & ACPI_APMT_FLAGS_AFFINITY ;
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if (affinity_flag == ACPI_APMT_FLAGS_AFFINITY_PROC ) {
@@ -1131,7 +1111,7 @@ static int arm_cspmu_acpi_get_cpus(struct arm_cspmu *cspmu)
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}
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if (cpumask_empty (& cspmu -> associated_cpus )) {
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- dev_dbg (dev , "No cpu associated with the PMU\n" );
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+ dev_dbg (cspmu -> dev , "No cpu associated with the PMU\n" );
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return - ENODEV ;
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}
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