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Mani-Sadhasivammbgg
Mani-Sadhasivam
authored and
mbgg
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arm64: dts: mediatek: Add I2C support for MT6797 SoC
Add I2C support for Mediatek MT6797 SoC. There are a total of 8 I2C controllers in this SoC (2 being shared) and they are same as the controllers present in MT6577 SoC. Hence, the driver support is added with DT fallback method. As per the datasheet, there are controllers with _imm prefix like i2c2_imm and i2c3_imm. These appears to be in different memory regions but sharing the same pins with i2c2 and i2c3 respectively. Since there is no clear evidence of what they really are, I've adapted the numbering/naming scheme from the downstream code by Mediatek. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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‎arch/arm64/boot/dts/mediatek/mt6797.dtsi

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Original file line numberDiff line numberDiff line change
@@ -155,6 +155,62 @@
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<MT6797_GPIO233__FUNC_UTXD1>;
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};
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};
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i2c0_pins_a: i2c0 {
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pins0 {
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pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
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<MT6797_GPIO38__FUNC_SDA0_0>;
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};
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};
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i2c1_pins_a: i2c1 {
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pins1 {
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pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
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<MT6797_GPIO56__FUNC_SDA1_0>;
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};
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};
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i2c2_pins_a: i2c2 {
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pins2 {
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pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
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<MT6797_GPIO95__FUNC_SDA2_0>;
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};
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};
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i2c3_pins_a: i2c3 {
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pins3 {
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pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
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<MT6797_GPIO74__FUNC_SCL3_0>;
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};
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};
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i2c4_pins_a: i2c4 {
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pins4 {
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pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
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<MT6797_GPIO239__FUNC_SCL4_0>;
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};
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};
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i2c5_pins_a: i2c5 {
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pins5 {
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pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
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<MT6797_GPIO241__FUNC_SCL5_0>;
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};
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};
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i2c6_pins_a: i2c6 {
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pins6 {
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pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
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<MT6797_GPIO151__FUNC_SCL6_0>;
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};
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};
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i2c7_pins_a: i2c7 {
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pins7 {
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pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
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<MT6797_GPIO153__FUNC_SCL7_0>;
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};
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};
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};
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scpsys: power-controller@10006000 {
@@ -233,6 +289,170 @@
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <0>;
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reg = <0 0x11007000 0 0x1000>,
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<0 0x11000100 0 0x80>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C0>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <1>;
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reg = <0 0x11008000 0 0x1000>,
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<0 0x11000180 0 0x80>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C1>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c8: i2c@11009000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <8>;
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reg = <0 0x11009000 0 0x1000>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C2>,
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<&infrasys CLK_INFRA_AP_DMA>,
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<&infrasys CLK_INFRA_I2C2_ARB>;
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clock-names = "main", "dma", "arb";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c9: i2c@1100d000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <9>;
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reg = <0 0x1100d000 0 0x1000>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C3>,
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<&infrasys CLK_INFRA_AP_DMA>,
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<&infrasys CLK_INFRA_I2C3_ARB>;
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clock-names = "main", "dma", "arb";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@1100e000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <6>;
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reg = <0 0x1100e000 0 0x1000>,
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<0 0x11000500 0 0x80>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C_APPM>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c7: i2c@11010000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <7>;
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reg = <0 0x11010000 0 0x1000>,
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<0 0x11000580 0 0x80>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@11011000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <4>;
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reg = <0 0x11011000 0 0x1000>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C4>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11013000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <2>;
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reg = <0 0x11013000 0 0x1000>,
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<0 0x11000400 0 0x80>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
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<&infrasys CLK_INFRA_AP_DMA>,
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<&infrasys CLK_INFRA_I2C2_ARB>;
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clock-names = "main", "dma", "arb";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@11014000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <3>;
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reg = <0 0x11014000 0 0x1000>,
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<0 0x11000480 0 0x80>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
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<&infrasys CLK_INFRA_AP_DMA>,
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<&infrasys CLK_INFRA_I2C3_ARB>;
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clock-names = "main", "dma", "arb";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@1101c000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <5>;
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reg = <0 0x1101c000 0 0x1000>,
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<0 0x11000380 0 0x80>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C5>,
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<&infrasys CLK_INFRA_AP_DMA>;
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clock-names = "main", "dma";
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clock-div = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mmsys: mmsys_config@14000000 {
237457
compatible = "mediatek,mt6797-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;

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