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#define DTS_DR_OFFSET 0x1C
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#define DTS_SR_OFFSET 0x20
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#define DTS_ITENR_OFFSET 0x24
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- #define DTS_CIFR_OFFSET 0x28
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+ #define DTS_ICIFR_OFFSET 0x28
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/* DTS_CFGR1 register mask definitions */
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#define HSREF_CLK_DIV_MASK GENMASK(30, 24)
@@ -122,10 +122,10 @@ static irqreturn_t stm_thermal_alarm_irq_thread(int irq, void *sdata)
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value = readl_relaxed (sensor -> base + DTS_SR_OFFSET );
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if ((value & LOW_THRESHOLD ) == LOW_THRESHOLD )
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- writel_relaxed (LOW_THRESHOLD , sensor -> base + DTS_CIFR_OFFSET );
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+ writel_relaxed (LOW_THRESHOLD , sensor -> base + DTS_ICIFR_OFFSET );
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if ((value & HIGH_THRESHOLD ) == HIGH_THRESHOLD )
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- writel_relaxed (HIGH_THRESHOLD , sensor -> base + DTS_CIFR_OFFSET );
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+ writel_relaxed (HIGH_THRESHOLD , sensor -> base + DTS_ICIFR_OFFSET );
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thermal_zone_device_update (sensor -> th_dev , THERMAL_EVENT_UNSPECIFIED );
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@@ -347,7 +347,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
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*/
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/* Make sure LOW_THRESHOLD IT is clear before enabling */
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- writel_relaxed (LOW_THRESHOLD , sensor -> base + DTS_CIFR_OFFSET );
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+ writel_relaxed (LOW_THRESHOLD , sensor -> base + DTS_ICIFR_OFFSET );
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/* Enable IT generation for low threshold */
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value = readl_relaxed (sensor -> base + DTS_ITENR_OFFSET );
@@ -356,7 +356,7 @@ static int stm_enable_irq(struct stm_thermal_sensor *sensor)
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/* Enable the low temperature threshold if needed */
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if (sensor -> low_temp_enabled ) {
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/* Make sure HIGH_THRESHOLD IT is clear before enabling */
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- writel_relaxed (HIGH_THRESHOLD , sensor -> base + DTS_CIFR_OFFSET );
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+ writel_relaxed (HIGH_THRESHOLD , sensor -> base + DTS_ICIFR_OFFSET );
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/* Enable IT generation for high threshold */
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value |= HIGH_THRESHOLD ;
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