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70 | 70 |
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71 | 71 | __EFI_PE_HEADER
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72 | 72 |
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73 |
| - .section ".idmap.text","awx" |
| 73 | + .section ".idmap.text","a" |
74 | 74 |
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75 | 75 | /*
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76 | 76 | * The following callee saved general purpose registers are used on the
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@@ -99,7 +99,8 @@ SYM_CODE_START(primary_entry)
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99 | 99 | cbz x19, 0f
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100 | 100 | adrp x0, __idmap_text_start
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101 | 101 | adr_l x1, __idmap_text_end
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102 |
| - bl dcache_clean_poc |
| 102 | + adr_l x2, dcache_clean_poc |
| 103 | + blr x2 |
103 | 104 | 0: mov x0, x19
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104 | 105 | bl init_kernel_el // w0=cpu_boot_mode
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105 | 106 | mov x20, x0
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@@ -527,7 +528,7 @@ SYM_FUNC_END(__primary_switched)
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527 | 528 | * end early head section, begin head code that is also used for
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528 | 529 | * hotplug and needs to have the same protections as the text region
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529 | 530 | */
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530 |
| - .section ".idmap.text","awx" |
| 531 | + .section ".idmap.text","a" |
531 | 532 |
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532 | 533 | /*
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533 | 534 | * Starting from EL2 or EL1, configure the CPU to execute at the highest
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@@ -566,7 +567,8 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
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566 | 567 | cbz x0, 0f
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567 | 568 | adrp x0, __hyp_idmap_text_start
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568 | 569 | adr_l x1, __hyp_text_end
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569 |
| - bl dcache_clean_poc |
| 570 | + adr_l x2, dcache_clean_poc |
| 571 | + blr x2 |
570 | 572 | 0:
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571 | 573 | mov_q x0, HCR_HOST_NVHE_FLAGS
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572 | 574 | msr hcr_el2, x0
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@@ -728,7 +730,7 @@ SYM_FUNC_END(set_cpu_boot_mode_flag)
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728 | 730 | * Checks if the selected granule size is supported by the CPU.
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729 | 731 | * If it isn't, park the CPU
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730 | 732 | */
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731 |
| - .section ".idmap.text","awx" |
| 733 | + .section ".idmap.text","a" |
732 | 734 | SYM_FUNC_START(__enable_mmu)
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733 | 735 | mrs x3, ID_AA64MMFR0_EL1
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734 | 736 | ubfx x3, x3, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4
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