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86 | 86 | #define ARM_CPU_PART_CORTEX_X2 0xD48
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87 | 87 | #define ARM_CPU_PART_NEOVERSE_N2 0xD49
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88 | 88 | #define ARM_CPU_PART_CORTEX_A78C 0xD4B
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| 89 | +#define ARM_CPU_PART_CORTEX_X1C 0xD4C |
| 90 | +#define ARM_CPU_PART_CORTEX_X3 0xD4E |
89 | 91 | #define ARM_CPU_PART_NEOVERSE_V2 0xD4F
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| 92 | +#define ARM_CPU_PART_CORTEX_A720 0xD81 |
90 | 93 | #define ARM_CPU_PART_CORTEX_X4 0xD82
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91 | 94 | #define ARM_CPU_PART_NEOVERSE_V3 0xD84
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| 95 | +#define ARM_CPU_PART_CORTEX_X925 0xD85 |
| 96 | +#define ARM_CPU_PART_CORTEX_A725 0xD87 |
92 | 97 |
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93 | 98 | #define APM_CPU_PART_XGENE 0x000
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94 | 99 | #define APM_CPU_VAR_POTENZA 0x00
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162 | 167 | #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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163 | 168 | #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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164 | 169 | #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
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| 170 | +#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) |
| 171 | +#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) |
165 | 172 | #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
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| 173 | +#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) |
166 | 174 | #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
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167 | 175 | #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
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| 176 | +#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) |
| 177 | +#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) |
168 | 178 | #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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169 | 179 | #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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170 | 180 | #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
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