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dt-bindings: PCI: qcom,pcie-sc8180x: Move SC8180X to dedicated schema
Move SC8180X PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Link: https://lore.kernel.org/linux-pci/20240205-dt-bindings-pci-qcom-split-continued-v1-1-c333cab5eeea@linaro.org Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Rob Herring <[email protected]>
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‎Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC8180x PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <[email protected]>
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- Manivannan Sadhasivam <[email protected]>
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description:
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Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
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DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pcie-sc8180x
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: ref # REFERENCE clock
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- const: tbu # PCIe TBU clock
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interrupts:
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minItems: 8
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maxItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
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#include <dt-bindings/interconnect/qcom,sc8180x.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c00000 {
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compatible = "qcom,pcie-sc8180x";
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reg = <0 0x01c00000 0 0x3000>,
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<0 0x60000000 0 0xf1d>,
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<0 0x60000f20 0 0xa8>,
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<0 0x60001000 0 0x1000>,
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<0 0x60100000 0 0x100000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config";
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ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
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clock-names = "pipe",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"ref",
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"tbu";
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dma-coherent;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
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<0x100 &apps_smmu 0x1d81 0x1>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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power-domains = <&gcc PCIE_0_GDSC>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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};
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};

‎Documentation/devicetree/bindings/pci/qcom,pcie.yaml

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- qcom,pcie-qcs404
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- qcom,pcie-sa8775p
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- qcom,pcie-sc7280
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- qcom,pcie-sc8180x
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- qcom,pcie-sdm845
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- qcom,pcie-sdx55
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- items:
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enum:
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- qcom,pcie-sa8775p
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- qcom,pcie-sc7280
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- qcom,pcie-sc8180x
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- qcom,pcie-sdx55
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then:
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properties:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sc8180x
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then:
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properties:
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: ref # REFERENCE clock
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- const: tbu # PCIe TBU clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci # PCIe core reset
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- if:
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properties:
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compatible:
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- qcom,pcie-msm8996
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- qcom,pcie-sa8775p
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- qcom,pcie-sc7280
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- qcom,pcie-sc8180x
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- qcom,pcie-sdm845
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then:
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oneOf:

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