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ouptonMarc Zyngier
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KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system
One of the oddities of the architecture is that the AArch64 views of the AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any EL. Nonetheless, KVM exposes these registers to userspace for the sake of save/restore. It is possible that the UNKNOWN value could differ between systems, leading to a rejected write from userspace. Avoid the issue altogether by handling the AArch32 ID registers as RAZ/WI when on an AArch64-only system. Signed-off-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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arch/arm64/kvm/sys_regs.c

Lines changed: 43 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1144,6 +1144,20 @@ static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
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return 0;
11451145
}
11461146

1147+
static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1148+
const struct sys_reg_desc *r)
1149+
{
1150+
/*
1151+
* AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1152+
* EL. Promote to RAZ/WI in order to guarantee consistency between
1153+
* systems.
1154+
*/
1155+
if (!kvm_supports_32bit_el0())
1156+
return REG_RAZ | REG_USER_WI;
1157+
1158+
return id_visibility(vcpu, r);
1159+
}
1160+
11471161
static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *r)
11491163
{
@@ -1331,6 +1345,15 @@ static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
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.visibility = id_visibility, \
13321346
}
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1348+
/* sys_reg_desc initialiser for known cpufeature ID registers */
1349+
#define AA32_ID_SANITISED(name) { \
1350+
SYS_DESC(SYS_##name), \
1351+
.access = access_id_reg, \
1352+
.get_user = get_id_reg, \
1353+
.set_user = set_id_reg, \
1354+
.visibility = aa32_id_visibility, \
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}
1356+
13341357
/*
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* sys_reg_desc initialiser for architecturally unallocated cpufeature ID
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* register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
@@ -1418,33 +1441,33 @@ static const struct sys_reg_desc sys_reg_descs[] = {
14181441

14191442
/* AArch64 mappings of the AArch32 ID registers */
14201443
/* CRm=1 */
1421-
ID_SANITISED(ID_PFR0_EL1),
1422-
ID_SANITISED(ID_PFR1_EL1),
1423-
ID_SANITISED(ID_DFR0_EL1),
1444+
AA32_ID_SANITISED(ID_PFR0_EL1),
1445+
AA32_ID_SANITISED(ID_PFR1_EL1),
1446+
AA32_ID_SANITISED(ID_DFR0_EL1),
14241447
ID_HIDDEN(ID_AFR0_EL1),
1425-
ID_SANITISED(ID_MMFR0_EL1),
1426-
ID_SANITISED(ID_MMFR1_EL1),
1427-
ID_SANITISED(ID_MMFR2_EL1),
1428-
ID_SANITISED(ID_MMFR3_EL1),
1448+
AA32_ID_SANITISED(ID_MMFR0_EL1),
1449+
AA32_ID_SANITISED(ID_MMFR1_EL1),
1450+
AA32_ID_SANITISED(ID_MMFR2_EL1),
1451+
AA32_ID_SANITISED(ID_MMFR3_EL1),
14291452

14301453
/* CRm=2 */
1431-
ID_SANITISED(ID_ISAR0_EL1),
1432-
ID_SANITISED(ID_ISAR1_EL1),
1433-
ID_SANITISED(ID_ISAR2_EL1),
1434-
ID_SANITISED(ID_ISAR3_EL1),
1435-
ID_SANITISED(ID_ISAR4_EL1),
1436-
ID_SANITISED(ID_ISAR5_EL1),
1437-
ID_SANITISED(ID_MMFR4_EL1),
1438-
ID_SANITISED(ID_ISAR6_EL1),
1454+
AA32_ID_SANITISED(ID_ISAR0_EL1),
1455+
AA32_ID_SANITISED(ID_ISAR1_EL1),
1456+
AA32_ID_SANITISED(ID_ISAR2_EL1),
1457+
AA32_ID_SANITISED(ID_ISAR3_EL1),
1458+
AA32_ID_SANITISED(ID_ISAR4_EL1),
1459+
AA32_ID_SANITISED(ID_ISAR5_EL1),
1460+
AA32_ID_SANITISED(ID_MMFR4_EL1),
1461+
AA32_ID_SANITISED(ID_ISAR6_EL1),
14391462

14401463
/* CRm=3 */
1441-
ID_SANITISED(MVFR0_EL1),
1442-
ID_SANITISED(MVFR1_EL1),
1443-
ID_SANITISED(MVFR2_EL1),
1464+
AA32_ID_SANITISED(MVFR0_EL1),
1465+
AA32_ID_SANITISED(MVFR1_EL1),
1466+
AA32_ID_SANITISED(MVFR2_EL1),
14441467
ID_UNALLOCATED(3,3),
1445-
ID_SANITISED(ID_PFR2_EL1),
1468+
AA32_ID_SANITISED(ID_PFR2_EL1),
14461469
ID_HIDDEN(ID_DFR1_EL1),
1447-
ID_SANITISED(ID_MMFR5_EL1),
1470+
AA32_ID_SANITISED(ID_MMFR5_EL1),
14481471
ID_UNALLOCATED(3,7),
14491472

14501473
/* AArch64 ID registers */

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