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Merge tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: - ARM SMMU and Mediatek updates from Will Deacon: - Support for MT8192 IOMMU from Mediatek - Arm v7s io-pgtable extensions for MT8192 - Removal of TLBI_ON_MAP quirk - New Qualcomm compatible strings - Allow SVA without hardware broadcast TLB maintenance on SMMUv3 - Virtualization Host Extension support for SMMUv3 (SVA) - Allow SMMUv3 PMU perf driver to be built independently from IOMMU - Some tidy-up in IOVA and core code - Conversion of the AMD IOMMU code to use the generic IO-page-table framework - Intel VT-d updates from Lu Baolu: - Audit capability consistency among different IOMMUs - Add SATC reporting structure support - Add iotlb_sync_map callback support - SDHI support for Renesas IOMMU driver - Misc cleanups and other small improvments * tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits) iommu/amd: Fix performance counter initialization MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER iommu/mediatek: Fix error code in probe() iommu/mediatek: Fix unsigned domid comparison with less than zero iommu/vt-d: Parse SATC reporting structure iommu/vt-d: Add new enum value and structure for SATC iommu/vt-d: Add iotlb_sync_map callback iommu/vt-d: Move capability check code to cap_audit files iommu/vt-d: Audit IOMMU Capabilities and add helper functions iommu/vt-d: Fix 'physical' typos iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration] driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3 MAINTAINERS: Add entry for MediaTek IOMMU iommu/mediatek: Add mt8192 support iommu/mediatek: Remove unnecessary check in attach_device iommu/mediatek: Support master use iova over 32bit iommu/mediatek: Add iova reserved function iommu/mediatek: Support for multi domains iommu/mediatek: Add get_domain_id from dev->dma_range_map ...
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‎Documentation/devicetree/bindings/iommu/arm,smmu.yaml

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@@ -34,9 +34,11 @@ properties:
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items:
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- enum:
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- qcom,sc7180-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sdm845-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,smmu-v2"
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items:

‎Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

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‎Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek IOMMU Architecture Implementation
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maintainers:
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- Yong Wu <[email protected]>
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description: |+
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Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
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this M4U have two generations of HW architecture. Generation one uses flat
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pagetable, and only supports 4K size page mapping. Generation two uses the
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ARM Short-Descriptor translation table format for address translation.
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About the M4U Hardware Block Diagram, please check below:
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EMI (External Memory Interface)
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|
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m4u (Multimedia Memory Management Unit)
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|
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+--------+
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| |
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gals0-rx gals1-rx (Global Async Local Sync rx)
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| |
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| |
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gals0-tx gals1-tx (Global Async Local Sync tx)
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| | Some SoCs may have GALS.
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+--------+
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|
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SMI Common(Smart Multimedia Interface Common)
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|
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+----------------+-------
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| |
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| gals-rx There may be GALS in some larbs.
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| |
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| |
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| gals-tx
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| |
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SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
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(display) (vdec)
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| |
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| |
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+-----+-----+ +----+----+
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| | | | | |
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| | |... | | | ... There are different ports in each larb.
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| | | | | |
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OVL0 RDMA0 WDMA0 MC PP VLD
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As above, The Multimedia HW will go through SMI and M4U while it
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access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
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smi local arbiter and smi common. It will control whether the Multimedia
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HW should go though the m4u for translation or bypass it and talk
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directly with EMI. And also SMI help control the power domain and clocks for
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each local arbiter.
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Normally we specify a local arbiter(larb) for each multimedia HW
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like display, video decode, and camera. And there are different ports
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in each larb. Take a example, There are many ports like MC, PP, VLD in the
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video decode local arbiter, all these ports are according to the video HW.
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In some SoCs, there may be a GALS(Global Async Local Sync) module between
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smi-common and m4u, and additional GALS module between smi-larb and
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smi-common. GALS can been seen as a "asynchronous fifo" which could help
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synchronize for the modules in different clock frequency.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-m4u # generation one
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- mediatek,mt2712-m4u # generation two
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- mediatek,mt6779-m4u # generation two
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- mediatek,mt8167-m4u # generation two
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- mediatek,mt8173-m4u # generation two
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- mediatek,mt8183-m4u # generation two
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- mediatek,mt8192-m4u # generation two
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- description: mt7623 generation one
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items:
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- const: mediatek,mt7623-m4u
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- const: mediatek,mt2701-m4u
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: bclk is the block clock.
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clock-names:
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items:
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- const: bclk
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mediatek,larbs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 32
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description: |
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List of phandle to the local arbiters in the current Socs.
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Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
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according to the local arbiter index, like larb0, larb1, larb2...
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'#iommu-cells':
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const: 1
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description: |
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This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
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defined in
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dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
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dt-binding/memory/mt2712-larb-port.h for mt2712,
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dt-binding/memory/mt6779-larb-port.h for mt6779,
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dt-binding/memory/mt8167-larb-port.h for mt8167,
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dt-binding/memory/mt8173-larb-port.h for mt8173,
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dt-binding/memory/mt8183-larb-port.h for mt8183,
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dt-binding/memory/mt8192-larb-port.h for mt8192.
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- mediatek,larbs
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- '#iommu-cells'
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt2701-m4u
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- mediatek,mt2712-m4u
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- mediatek,mt8173-m4u
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- mediatek,mt8192-m4u
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then:
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required:
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- clocks
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- if:
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properties:
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compatible:
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enum:
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- mediatek,mt8192-m4u
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then:
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required:
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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iommu: iommu@10205000 {
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compatible = "mediatek,mt8173-m4u";
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reg = <0x10205000 0x1000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2
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&larb3 &larb4 &larb5>;
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#iommu-cells = <1>;
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};
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- |
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#include <dt-bindings/memory/mt8173-larb-port.h>
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/* Example for a client device */
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display {
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compatible = "mediatek,mt8173-disp";
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iommus = <&iommu M4U_PORT_DISP_OVL0>,
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<&iommu M4U_PORT_DISP_RDMA0>;
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};

‎MAINTAINERS

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F: Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
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F: drivers/i2c/busses/i2c-mt65xx.c
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MEDIATEK IOMMU DRIVER
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M: Yong Wu <[email protected]>
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L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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S: Supported
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F: Documentation/devicetree/bindings/iommu/mediatek*
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F: drivers/iommu/mtk_iommu*
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F: include/dt-bindings/memory/mt*-port.h
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MEDIATEK JPEG DRIVER
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M: Rick Chang <[email protected]>
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M: Bin Liu <[email protected]>

‎drivers/iommu/amd/Kconfig

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select IOMMU_API
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select IOMMU_IOVA
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select IOMMU_DMA
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select IOMMU_IO_PGTABLE
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depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
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help
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With this option you can enable support for AMD IOMMU hardware in

‎drivers/iommu/amd/Makefile

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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_AMD_IOMMU) += iommu.o init.o quirks.o
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obj-$(CONFIG_AMD_IOMMU) += iommu.o init.o quirks.o io_pgtable.o
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obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o
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obj-$(CONFIG_AMD_IOMMU_V2) += iommu_v2.o

‎drivers/iommu/amd/amd_iommu.h

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extern int amd_iommu_reenable(int);
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extern int amd_iommu_enable_faulting(void);
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extern int amd_iommu_guest_ir;
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extern enum io_pgtable_fmt amd_iommu_pgtable;
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/* IOMMUv2 specific functions */
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struct iommu_domain;
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extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
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extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
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u64 address);
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extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
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extern void amd_iommu_domain_update(struct protection_domain *domain);
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extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
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extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
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extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
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extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
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unsigned long cr3);
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return phys_to_virt(__sme_clr(paddr));
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}
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static inline
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void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
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{
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atomic64_set(&domain->iop.pt_root, root);
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domain->iop.root = (u64 *)(root & PAGE_MASK);
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domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
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}
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static inline
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void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
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{
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amd_iommu_domain_set_pt_root(domain, 0);
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}
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extern bool translation_pre_enabled(struct amd_iommu *iommu);
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extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
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struct device *dev);
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
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u64 *root, int mode);
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#endif

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