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Jane Jianalexdeucher
Jane Jian
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alexdeucher
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drm/amdgpu/vcn: custom video info caps for sriov
for sriov, we added a new flag to indicate av1 support, this will override the original caps info. Signed-off-by: Jane Jian <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-11
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3 files changed

+99
-11
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,8 @@ enum AMDGIM_FEATURE_FLAG {
124124
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
125125
/* Indirect Reg Access enabled */
126126
AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
127+
/* AV1 Support MODE*/
128+
AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
127129
};
128130

129131
enum AMDGIM_REG_ACCESS_FLAG {
@@ -322,6 +324,8 @@ static inline bool is_virtual_machine(void)
322324
((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
323325
#define amdgpu_sriov_is_normal(adev) \
324326
((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
327+
#define amdgpu_sriov_is_av1_support(adev) \
328+
((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
325329
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
326330
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
327331
void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,8 @@ union amd_sriov_msg_feature_flags {
9393
uint32_t mm_bw_management : 1;
9494
uint32_t pp_one_vf_mode : 1;
9595
uint32_t reg_indirect_acc : 1;
96-
uint32_t reserved : 26;
96+
uint32_t av1_support : 1;
97+
uint32_t reserved : 25;
9798
} flags;
9899
uint32_t all;
99100
};

‎drivers/gpu/drm/amd/amdgpu/soc21.c

Lines changed: 93 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,59 @@ static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
102102
.codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
103103
};
104104

105+
/* SRIOV SOC21, not const since data is controlled by host */
106+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
107+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
108+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
109+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
110+
};
111+
112+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
113+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
114+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
115+
};
116+
117+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
118+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
119+
.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
120+
};
121+
122+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
123+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
124+
.codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
125+
};
126+
127+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
128+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
129+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
130+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
131+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
132+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
136+
};
137+
138+
static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
139+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
140+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
141+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
142+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
143+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
144+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
145+
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
146+
};
147+
148+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
149+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
150+
.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
151+
};
152+
153+
static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
154+
.codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
155+
.codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
156+
};
157+
105158
static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
106159
const struct amdgpu_video_codecs **codecs)
107160
{
@@ -112,16 +165,31 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
112165
case IP_VERSION(4, 0, 0):
113166
case IP_VERSION(4, 0, 2):
114167
case IP_VERSION(4, 0, 4):
115-
if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
116-
if (encode)
117-
*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
118-
else
119-
*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
168+
if (amdgpu_sriov_vf(adev)) {
169+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
170+
!amdgpu_sriov_is_av1_support(adev)) {
171+
if (encode)
172+
*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
173+
else
174+
*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
175+
} else {
176+
if (encode)
177+
*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
178+
else
179+
*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
180+
}
120181
} else {
121-
if (encode)
122-
*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
123-
else
124-
*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
182+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
183+
if (encode)
184+
*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
185+
else
186+
*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
187+
} else {
188+
if (encode)
189+
*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
190+
else
191+
*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
192+
}
125193
}
126194
return 0;
127195
default:
@@ -730,8 +798,23 @@ static int soc21_common_late_init(void *handle)
730798
{
731799
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
732800

733-
if (amdgpu_sriov_vf(adev))
801+
if (amdgpu_sriov_vf(adev)) {
734802
xgpu_nv_mailbox_get_irq(adev);
803+
if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
804+
!amdgpu_sriov_is_av1_support(adev)) {
805+
amdgpu_virt_update_sriov_video_codec(adev,
806+
sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
807+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
808+
sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
809+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
810+
} else {
811+
amdgpu_virt_update_sriov_video_codec(adev,
812+
sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
813+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
814+
sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
815+
ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
816+
}
817+
}
735818

736819
return 0;
737820
}

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