@@ -5,7 +5,7 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Mediatek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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- generation 2: mt2712, mt8173 and mt8183.
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+ generation 2: mt2712, mt6779, mt8173 and mt8183.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
@@ -18,6 +18,7 @@ Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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+ "mediatek,mt6779-smi-common"
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"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
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"mediatek,mt8173-smi-common"
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"mediatek,mt8183-smi-common"
@@ -35,7 +36,7 @@ Required properties:
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and these 2 option clocks for generation 2 smi HW:
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- "gals0": the path0 clock of GALS(Global Async Local Sync).
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- "gals1": the path1 clock of GALS(Global Async Local Sync).
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- Here is the list which has this GALS: mt8183.
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+ Here is the list which has this GALS: mt6779 and mt8183.
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Example:
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smi_common: smi@14022000 {
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