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#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
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#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
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#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K 1
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K 2
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K 3
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K 4
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#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
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#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
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#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
@@ -407,6 +411,7 @@ struct wsa_macro {
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int ear_spkr_gain ;
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int spkr_gain_offset ;
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int spkr_mode ;
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+ u32 pcm_rate_vi ;
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int is_softclip_on [WSA_MACRO_SOFTCLIP_MAX ];
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int softclip_clk_users [WSA_MACRO_SOFTCLIP_MAX ];
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struct regmap * regmap ;
@@ -1280,6 +1285,7 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai * dai )
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{
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struct snd_soc_component * component = dai -> component ;
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+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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int ret ;
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switch (substream -> stream ) {
@@ -1291,6 +1297,11 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
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__func__ , params_rate (params ));
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return ret ;
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}
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+ break ;
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+ case SNDRV_PCM_STREAM_CAPTURE :
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+ if (dai -> id == WSA_MACRO_AIF_VI )
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+ wsa -> pcm_rate_vi = params_rate (params );
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+
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break ;
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default :
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break ;
@@ -1465,6 +1476,28 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
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struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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u32 tx_reg0 , tx_reg1 ;
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+ u32 rate_val ;
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+
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+ switch (wsa -> pcm_rate_vi ) {
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+ case 8000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
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+ break ;
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+ case 16000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K ;
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+ break ;
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+ case 24000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K ;
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+ break ;
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+ case 32000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K ;
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+ break ;
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+ case 48000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K ;
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+ break ;
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+ default :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
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+ break ;
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+ }
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if (test_bit (WSA_MACRO_TX0 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ])) {
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tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL ;
@@ -1476,7 +1509,7 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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switch (event ) {
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case SND_SOC_DAPM_POST_PMU :
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- /* Enable V&I sensing */
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+ /* Enable V&I sensing */
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_RESET_MASK ,
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CDC_WSA_TX_SPKR_PROT_RESET );
@@ -1485,10 +1518,10 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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CDC_WSA_TX_SPKR_PROT_RESET );
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
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- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
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+ rate_val );
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snd_soc_component_update_bits (component , tx_reg1 ,
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CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
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- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
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+ rate_val );
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK ,
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CDC_WSA_TX_SPKR_PROT_CLK_ENABLE );
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