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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Samsung MIPI DSIM bridge controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + |
| 12 | + - Marek Szyprowski <[email protected]> |
| 13 | + |
| 14 | +description: | |
| 15 | + Samsung MIPI DSIM bridge controller can be found it on Exynos |
| 16 | + and i.MX8M Mini/Nano/Plus SoC's. |
| 17 | +
|
| 18 | +properties: |
| 19 | + compatible: |
| 20 | + oneOf: |
| 21 | + - enum: |
| 22 | + - samsung,exynos3250-mipi-dsi |
| 23 | + - samsung,exynos4210-mipi-dsi |
| 24 | + - samsung,exynos5410-mipi-dsi |
| 25 | + - samsung,exynos5422-mipi-dsi |
| 26 | + - samsung,exynos5433-mipi-dsi |
| 27 | + - fsl,imx8mm-mipi-dsim |
| 28 | + - fsl,imx8mp-mipi-dsim |
| 29 | + - items: |
| 30 | + - const: fsl,imx8mn-mipi-dsim |
| 31 | + - const: fsl,imx8mm-mipi-dsim |
| 32 | + |
| 33 | + reg: |
| 34 | + maxItems: 1 |
| 35 | + |
| 36 | + interrupts: |
| 37 | + maxItems: 1 |
| 38 | + |
| 39 | + '#address-cells': |
| 40 | + const: 1 |
| 41 | + |
| 42 | + '#size-cells': |
| 43 | + const: 0 |
| 44 | + |
| 45 | + clocks: |
| 46 | + minItems: 2 |
| 47 | + maxItems: 5 |
| 48 | + |
| 49 | + clock-names: |
| 50 | + minItems: 2 |
| 51 | + maxItems: 5 |
| 52 | + |
| 53 | + samsung,phy-type: |
| 54 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 55 | + description: phandle to the samsung phy-type |
| 56 | + |
| 57 | + power-domains: |
| 58 | + maxItems: 1 |
| 59 | + |
| 60 | + samsung,power-domain: |
| 61 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 62 | + description: phandle to the associated samsung power domain |
| 63 | + |
| 64 | + vddcore-supply: |
| 65 | + description: MIPI DSIM Core voltage supply (e.g. 1.1V) |
| 66 | + |
| 67 | + vddio-supply: |
| 68 | + description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) |
| 69 | + |
| 70 | + samsung,burst-clock-frequency: |
| 71 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 72 | + description: |
| 73 | + DSIM high speed burst mode frequency. |
| 74 | + |
| 75 | + samsung,esc-clock-frequency: |
| 76 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 77 | + description: |
| 78 | + DSIM escape mode frequency. |
| 79 | + |
| 80 | + samsung,pll-clock-frequency: |
| 81 | + $ref: /schemas/types.yaml#/definitions/uint32 |
| 82 | + description: |
| 83 | + DSIM oscillator clock frequency. |
| 84 | + |
| 85 | + phys: |
| 86 | + maxItems: 1 |
| 87 | + |
| 88 | + phy-names: |
| 89 | + const: dsim |
| 90 | + |
| 91 | + ports: |
| 92 | + $ref: /schemas/graph.yaml#/properties/ports |
| 93 | + |
| 94 | + properties: |
| 95 | + port@0: |
| 96 | + $ref: /schemas/graph.yaml#/properties/port |
| 97 | + description: |
| 98 | + Input port node to receive pixel data from the |
| 99 | + display controller. Exactly one endpoint must be |
| 100 | + specified. |
| 101 | + |
| 102 | + port@1: |
| 103 | + $ref: /schemas/graph.yaml#/properties/port |
| 104 | + description: |
| 105 | + DSI output port node to the panel or the next bridge |
| 106 | + in the chain. |
| 107 | + |
| 108 | +required: |
| 109 | + - clock-names |
| 110 | + - clocks |
| 111 | + - compatible |
| 112 | + - interrupts |
| 113 | + - reg |
| 114 | + - samsung,burst-clock-frequency |
| 115 | + - samsung,esc-clock-frequency |
| 116 | + - samsung,pll-clock-frequency |
| 117 | + |
| 118 | +allOf: |
| 119 | + - $ref: ../dsi-controller.yaml# |
| 120 | + - if: |
| 121 | + properties: |
| 122 | + compatible: |
| 123 | + contains: |
| 124 | + const: samsung,exynos5433-mipi-dsi |
| 125 | + |
| 126 | + then: |
| 127 | + properties: |
| 128 | + clocks: |
| 129 | + minItems: 5 |
| 130 | + |
| 131 | + clock-names: |
| 132 | + items: |
| 133 | + - const: bus_clk |
| 134 | + - const: phyclk_mipidphy0_bitclkdiv8 |
| 135 | + - const: phyclk_mipidphy0_rxclkesc0 |
| 136 | + - const: sclk_rgb_vclk_to_dsim0 |
| 137 | + - const: sclk_mipi |
| 138 | + |
| 139 | + ports: |
| 140 | + required: |
| 141 | + - port@0 |
| 142 | + |
| 143 | + required: |
| 144 | + - ports |
| 145 | + - vddcore-supply |
| 146 | + - vddio-supply |
| 147 | + |
| 148 | + - if: |
| 149 | + properties: |
| 150 | + compatible: |
| 151 | + contains: |
| 152 | + const: samsung,exynos5410-mipi-dsi |
| 153 | + |
| 154 | + then: |
| 155 | + properties: |
| 156 | + clocks: |
| 157 | + minItems: 2 |
| 158 | + |
| 159 | + clock-names: |
| 160 | + items: |
| 161 | + - const: bus_clk |
| 162 | + - const: pll_clk |
| 163 | + |
| 164 | + required: |
| 165 | + - vddcore-supply |
| 166 | + - vddio-supply |
| 167 | + |
| 168 | + - if: |
| 169 | + properties: |
| 170 | + compatible: |
| 171 | + contains: |
| 172 | + const: samsung,exynos4210-mipi-dsi |
| 173 | + |
| 174 | + then: |
| 175 | + properties: |
| 176 | + clocks: |
| 177 | + minItems: 2 |
| 178 | + |
| 179 | + clock-names: |
| 180 | + items: |
| 181 | + - const: bus_clk |
| 182 | + - const: sclk_mipi |
| 183 | + |
| 184 | + required: |
| 185 | + - vddcore-supply |
| 186 | + - vddio-supply |
| 187 | + |
| 188 | + - if: |
| 189 | + properties: |
| 190 | + compatible: |
| 191 | + contains: |
| 192 | + const: samsung,exynos3250-mipi-dsi |
| 193 | + |
| 194 | + then: |
| 195 | + properties: |
| 196 | + clocks: |
| 197 | + minItems: 2 |
| 198 | + |
| 199 | + clock-names: |
| 200 | + items: |
| 201 | + - const: bus_clk |
| 202 | + - const: pll_clk |
| 203 | + |
| 204 | + required: |
| 205 | + - vddcore-supply |
| 206 | + - vddio-supply |
| 207 | + - samsung,phy-type |
| 208 | + |
| 209 | +additionalProperties: |
| 210 | + type: object |
| 211 | + |
| 212 | +examples: |
| 213 | + - | |
| 214 | + #include <dt-bindings/clock/exynos5433.h> |
| 215 | + #include <dt-bindings/gpio/gpio.h> |
| 216 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 217 | +
|
| 218 | + dsi@13900000 { |
| 219 | + compatible = "samsung,exynos5433-mipi-dsi"; |
| 220 | + reg = <0x13900000 0xC0>; |
| 221 | + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 222 | + phys = <&mipi_phy 1>; |
| 223 | + phy-names = "dsim"; |
| 224 | + clocks = <&cmu_disp CLK_PCLK_DSIM0>, |
| 225 | + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, |
| 226 | + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, |
| 227 | + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, |
| 228 | + <&cmu_disp CLK_SCLK_DSIM0>; |
| 229 | + clock-names = "bus_clk", |
| 230 | + "phyclk_mipidphy0_bitclkdiv8", |
| 231 | + "phyclk_mipidphy0_rxclkesc0", |
| 232 | + "sclk_rgb_vclk_to_dsim0", |
| 233 | + "sclk_mipi"; |
| 234 | + power-domains = <&pd_disp>; |
| 235 | + vddcore-supply = <&ldo6_reg>; |
| 236 | + vddio-supply = <&ldo7_reg>; |
| 237 | + samsung,burst-clock-frequency = <512000000>; |
| 238 | + samsung,esc-clock-frequency = <16000000>; |
| 239 | + samsung,pll-clock-frequency = <24000000>; |
| 240 | + pinctrl-names = "default"; |
| 241 | + pinctrl-0 = <&te_irq>; |
| 242 | +
|
| 243 | + ports { |
| 244 | + #address-cells = <1>; |
| 245 | + #size-cells = <0>; |
| 246 | +
|
| 247 | + port@0 { |
| 248 | + reg = <0>; |
| 249 | +
|
| 250 | + dsi_to_mic: endpoint { |
| 251 | + remote-endpoint = <&mic_to_dsi>; |
| 252 | + }; |
| 253 | + }; |
| 254 | + }; |
| 255 | + }; |
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