@@ -252,7 +252,7 @@ static int am33xx_pm_begin(suspend_state_t state)
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if (state == PM_SUSPEND_MEM && pm_ops -> check_off_mode_enable ()) {
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nvmem = devm_nvmem_device_get (& omap_rtc -> dev ,
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"omap_rtc_scratch0" );
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- if (nvmem )
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+ if (! IS_ERR ( nvmem ) )
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nvmem_device_write (nvmem , RTC_SCRATCH_MAGIC_REG * 4 , 4 ,
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(void * )& rtc_magic_val );
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rtc_only_idle = 1 ;
@@ -278,9 +278,12 @@ static void am33xx_pm_end(void)
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struct nvmem_device * nvmem ;
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nvmem = devm_nvmem_device_get (& omap_rtc -> dev , "omap_rtc_scratch0" );
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+ if (IS_ERR (nvmem ))
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+ return ;
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+
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m3_ipc -> ops -> finish_low_power (m3_ipc );
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if (rtc_only_idle ) {
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- if (retrigger_irq )
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+ if (retrigger_irq ) {
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/*
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* 32 bits of Interrupt Set-Pending correspond to 32
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* 32 interrupts. Compute the bit offset of the
@@ -291,8 +294,10 @@ static void am33xx_pm_end(void)
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writel_relaxed (1 << (retrigger_irq & 31 ),
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gic_dist_base + GIC_INT_SET_PENDING_BASE
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+ retrigger_irq / 32 * 4 );
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- nvmem_device_write (nvmem , RTC_SCRATCH_MAGIC_REG * 4 , 4 ,
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- (void * )& val );
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+ }
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+
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+ nvmem_device_write (nvmem , RTC_SCRATCH_MAGIC_REG * 4 , 4 ,
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+ (void * )& val );
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}
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rtc_only_idle = 0 ;
@@ -415,7 +420,7 @@ static int am33xx_pm_rtc_setup(void)
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nvmem = devm_nvmem_device_get (& omap_rtc -> dev ,
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"omap_rtc_scratch0" );
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- if (nvmem ) {
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+ if (! IS_ERR ( nvmem ) ) {
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nvmem_device_read (nvmem , RTC_SCRATCH_MAGIC_REG * 4 ,
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4 , (void * )& rtc_magic_val );
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if ((rtc_magic_val & 0xffff ) != RTC_REG_BOOT_MAGIC )
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