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abelvesavinodkoul
abelvesa
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vinodkoul
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phy: qcom: edp: Add v6 specific ops and X1E80100 platform support
Add v6 HW support by implementing the version ops. Add the X1E80100 compatible and match config as it is v6. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-edp.c

Lines changed: 180 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
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#include "phy-qcom-qmp-dp-phy.h"
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#include "phy-qcom-qmp-qserdes-com-v4.h"
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#include "phy-qcom-qmp-qserdes-com-v6.h"
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/* EDP_PHY registers */
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#define DP_PHY_CFG 0x0010
@@ -532,6 +533,184 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
532533
.ver_ops = &qcom_edp_phy_ops_v4,
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};
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536+
static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp)
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{
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u32 val;
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writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
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DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
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DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
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edp->edp + DP_PHY_PD_CTL);
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writel(0xfc, edp->edp + DP_PHY_MODE);
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return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS,
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val, val & BIT(7), 5, 200);
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}
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static int qcom_edp_phy_com_resetsm_cntrl_v6(const struct qcom_edp *edp)
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{
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u32 val;
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writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL);
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return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS,
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val, val & BIT(0), 500, 10000);
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}
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static int qcom_edp_com_bias_en_clkbuflr_v6(const struct qcom_edp *edp)
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{
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/* Turn on BIAS current for PHY/PLL */
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writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
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return 0;
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}
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static int qcom_edp_com_configure_ssc_v6(const struct qcom_edp *edp)
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{
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const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
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u32 step1;
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u32 step2;
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switch (dp_opts->link_rate) {
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case 1620:
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case 2700:
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case 8100:
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step1 = 0x92;
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step2 = 0x01;
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break;
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case 5400:
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step1 = 0x18;
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step2 = 0x02;
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break;
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default:
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/* Other link rates aren't supported */
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return -EINVAL;
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}
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writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER);
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writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1);
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writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1);
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writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2);
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writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0);
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writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0);
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return 0;
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}
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static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp)
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{
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const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
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u32 div_frac_start2_mode0;
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u32 div_frac_start3_mode0;
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u32 dec_start_mode0;
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u32 lock_cmp1_mode0;
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u32 lock_cmp2_mode0;
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u32 code1_mode0;
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u32 code2_mode0;
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u32 hsclk_sel;
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switch (dp_opts->link_rate) {
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case 1620:
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hsclk_sel = 0x5;
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dec_start_mode0 = 0x34;
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div_frac_start2_mode0 = 0xc0;
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div_frac_start3_mode0 = 0x0b;
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lock_cmp1_mode0 = 0x37;
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lock_cmp2_mode0 = 0x04;
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code1_mode0 = 0x71;
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code2_mode0 = 0x0c;
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break;
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case 2700:
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hsclk_sel = 0x3;
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dec_start_mode0 = 0x34;
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div_frac_start2_mode0 = 0xc0;
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div_frac_start3_mode0 = 0x0b;
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lock_cmp1_mode0 = 0x07;
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lock_cmp2_mode0 = 0x07;
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code1_mode0 = 0x71;
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code2_mode0 = 0x0c;
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break;
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637+
case 5400:
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hsclk_sel = 0x1;
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dec_start_mode0 = 0x46;
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div_frac_start2_mode0 = 0x00;
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div_frac_start3_mode0 = 0x05;
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lock_cmp1_mode0 = 0x0f;
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lock_cmp2_mode0 = 0x0e;
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code1_mode0 = 0x97;
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code2_mode0 = 0x10;
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break;
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case 8100:
649+
hsclk_sel = 0x0;
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dec_start_mode0 = 0x34;
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div_frac_start2_mode0 = 0xc0;
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div_frac_start3_mode0 = 0x0b;
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lock_cmp1_mode0 = 0x17;
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lock_cmp2_mode0 = 0x15;
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code1_mode0 = 0x71;
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code2_mode0 = 0x0c;
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break;
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default:
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/* Other link rates aren't supported */
661+
return -EINVAL;
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}
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writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL);
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writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL);
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writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL);
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writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1);
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writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE);
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writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT);
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writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1);
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writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO);
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writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN);
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writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0);
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writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0);
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writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0);
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writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0);
677+
writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0);
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writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0);
679+
writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0);
680+
writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1);
681+
writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0);
682+
writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0);
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writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP);
684+
writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0);
685+
writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0);
686+
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writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER);
688+
writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0);
689+
writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL);
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writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
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writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN);
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writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0);
693+
writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0);
694+
695+
writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
696+
writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
697+
698+
return 0;
699+
}
700+
701+
static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
702+
.com_power_on = qcom_edp_phy_power_on_v6,
703+
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v6,
704+
.com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v6,
705+
.com_configure_pll = qcom_edp_com_configure_pll_v6,
706+
.com_configure_ssc = qcom_edp_com_configure_ssc_v6,
707+
};
708+
709+
static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
710+
.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
711+
.ver_ops = &qcom_edp_phy_ops_v6,
712+
};
713+
535714
static int qcom_edp_phy_power_on(struct phy *phy)
536715
{
537716
const struct qcom_edp *edp = phy_get_drvdata(phy);
@@ -933,6 +1112,7 @@ static const struct of_device_id qcom_edp_phy_match_table[] = {
9331112
{ .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
9341113
{ .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },
9351114
{ .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
1115+
{ .compatible = "qcom,x1e80100-dp-phy", .data = &x1e80100_phy_cfg, },
9361116
{ }
9371117
};
9381118
MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table);

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