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18 | 18 | /* SEV Information Request/Response */
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19 | 19 | #define GHCB_MSR_SEV_INFO_RESP 0x001
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20 | 20 | #define GHCB_MSR_SEV_INFO_REQ 0x002
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21 |
| -#define GHCB_MSR_VER_MAX_POS 48 |
22 |
| -#define GHCB_MSR_VER_MAX_MASK 0xffff |
23 |
| -#define GHCB_MSR_VER_MIN_POS 32 |
24 |
| -#define GHCB_MSR_VER_MIN_MASK 0xffff |
25 |
| -#define GHCB_MSR_CBIT_POS 24 |
26 |
| -#define GHCB_MSR_CBIT_MASK 0xff |
27 |
| -#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ |
28 |
| - ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \ |
29 |
| - (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \ |
30 |
| - (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \ |
| 21 | + |
| 22 | +#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ |
| 23 | + /* GHCBData[63:48] */ \ |
| 24 | + ((((_max) & 0xffff) << 48) | \ |
| 25 | + /* GHCBData[47:32] */ \ |
| 26 | + (((_min) & 0xffff) << 32) | \ |
| 27 | + /* GHCBData[31:24] */ \ |
| 28 | + (((_cbit) & 0xff) << 24) | \ |
31 | 29 | GHCB_MSR_SEV_INFO_RESP)
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| 30 | + |
32 | 31 | #define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
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33 |
| -#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK) |
34 |
| -#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK) |
| 32 | +#define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) |
| 33 | +#define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) |
35 | 34 |
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36 | 35 | /* CPUID Request/Response */
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37 | 36 | #define GHCB_MSR_CPUID_REQ 0x004
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46 | 45 | #define GHCB_CPUID_REQ_EBX 1
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47 | 46 | #define GHCB_CPUID_REQ_ECX 2
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48 | 47 | #define GHCB_CPUID_REQ_EDX 3
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49 |
| -#define GHCB_CPUID_REQ(fn, reg) \ |
50 |
| - (GHCB_MSR_CPUID_REQ | \ |
51 |
| - (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ |
52 |
| - (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) |
| 48 | +#define GHCB_CPUID_REQ(fn, reg) \ |
| 49 | + /* GHCBData[11:0] */ \ |
| 50 | + (GHCB_MSR_CPUID_REQ | \ |
| 51 | + /* GHCBData[31:12] */ \ |
| 52 | + (((unsigned long)(reg) & 0x3) << 30) | \ |
| 53 | + /* GHCBData[63:32] */ \ |
| 54 | + (((unsigned long)fn) << 32)) |
53 | 55 |
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54 | 56 | /* AP Reset Hold */
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55 |
| -#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 |
56 |
| -#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 |
| 57 | +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 |
| 58 | +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 |
57 | 59 |
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58 | 60 | /* GHCB Hypervisor Feature Request/Response */
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59 |
| -#define GHCB_MSR_HV_FT_REQ 0x080 |
60 |
| -#define GHCB_MSR_HV_FT_RESP 0x081 |
| 61 | +#define GHCB_MSR_HV_FT_REQ 0x080 |
| 62 | +#define GHCB_MSR_HV_FT_RESP 0x081 |
61 | 63 |
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62 | 64 | #define GHCB_MSR_TERM_REQ 0x100
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63 | 65 | #define GHCB_MSR_TERM_REASON_SET_POS 12
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64 | 66 | #define GHCB_MSR_TERM_REASON_SET_MASK 0xf
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65 | 67 | #define GHCB_MSR_TERM_REASON_POS 16
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66 | 68 | #define GHCB_MSR_TERM_REASON_MASK 0xff
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67 |
| -#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ |
68 |
| - (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ |
69 |
| - ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) |
| 69 | + |
| 70 | +#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \ |
| 71 | + /* GHCBData[15:12] */ \ |
| 72 | + (((((u64)reason_set) & 0xf) << 12) | \ |
| 73 | + /* GHCBData[23:16] */ \ |
| 74 | + ((((u64)reason_val) & 0xff) << 16)) |
70 | 75 |
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71 | 76 | #define GHCB_SEV_ES_GEN_REQ 0
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72 | 77 | #define GHCB_SEV_ES_PROT_UNSUPPORTED 1
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