drm/i915/mtl: Fix HDMI/DP PLL clock selection

Select the HDMI specific PLL clock only for HDMI outputs.

Fixes: 62618c7 ("drm/i915/mtl: C20 PLL programming")
Cc: Mika Kahola <[email protected]>
Cc: Radhakrishna Sripada <[email protected]>
Reviewed-by: Radhakrishna Sripada <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit 937d02c)
Signed-off-by: Jani Nikula <[email protected]>

Author: ideak

drivers/gpu/drm/i915/display/intel_cx0_phy.c

@@ -2465,7 +2465,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
 
-	if (is_hdmi_frl(crtc_state->port_clock))
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+	    is_hdmi_frl(crtc_state->port_clock))
 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
 	else
 		val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);