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Harry Wentlandalexdeucher
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drm/amdgpu: Use correct VIEWPORT_DIMENSION for DCN2
For some reason this file isn't using the appropriate register headers for DCN headers, which means that on DCN2 we're getting the VIEWPORT_DIMENSION offset wrong. This means that we're not correctly carving out the framebuffer memory correctly for a framebuffer allocated by EFI and therefore see corruption when loading amdgpu before the display driver takes over control of the framebuffer scanout. Fix this by checking the DCE_HWIP and picking the correct offset accordingly. Long-term we should expose this info from DC as GMC shouldn't need to know about DCN registers. Cc: [email protected] Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,9 @@
7272
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
7373
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
7474

75+
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
76+
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
77+
7578

7679
static const char *gfxhub_client_ids[] = {
7780
"CB",
@@ -1134,6 +1137,8 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
11341137
u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
11351138
unsigned size;
11361139

1140+
/* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1141+
11371142
if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
11381143
size = AMDGPU_VBIOS_VGA_ALLOCATION;
11391144
} else {
@@ -1142,14 +1147,21 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
11421147
switch (adev->ip_versions[DCE_HWIP][0]) {
11431148
case IP_VERSION(1, 0, 0):
11441149
case IP_VERSION(1, 0, 1):
1145-
case IP_VERSION(2, 1, 0):
11461150
viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
11471151
size = (REG_GET_FIELD(viewport,
11481152
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
11491153
REG_GET_FIELD(viewport,
11501154
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
11511155
4);
11521156
break;
1157+
case IP_VERSION(2, 1, 0):
1158+
viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1159+
size = (REG_GET_FIELD(viewport,
1160+
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1161+
REG_GET_FIELD(viewport,
1162+
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1163+
4);
1164+
break;
11531165
default:
11541166
viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
11551167
size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *

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