@@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_1_0 * res = & pcie -> res .v2_1_0 ;
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+ clk_disable_unprepare (res -> phy_clk );
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reset_control_assert (res -> pci_reset );
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reset_control_assert (res -> axi_reset );
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reset_control_assert (res -> ahb_reset );
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reset_control_assert (res -> por_reset );
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- reset_control_assert (res -> pci_reset );
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+ reset_control_assert (res -> phy_reset );
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clk_disable_unprepare (res -> iface_clk );
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clk_disable_unprepare (res -> core_clk );
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- clk_disable_unprepare (res -> phy_clk );
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clk_disable_unprepare (res -> aux_clk );
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clk_disable_unprepare (res -> ref_clk );
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regulator_bulk_disable (ARRAY_SIZE (res -> supplies ), res -> supplies );
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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goto err_clk_core ;
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}
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- ret = clk_prepare_enable (res -> phy_clk );
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- if (ret ) {
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- dev_err (dev , "cannot prepare/enable phy clock\n" );
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- goto err_clk_phy ;
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- }
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-
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ret = clk_prepare_enable (res -> aux_clk );
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if (ret ) {
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dev_err (dev , "cannot prepare/enable aux clock\n" );
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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return ret ;
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}
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+ ret = clk_prepare_enable (res -> phy_clk );
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+ if (ret ) {
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+ dev_err (dev , "cannot prepare/enable phy clock\n" );
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+ goto err_deassert_ahb ;
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+ }
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+
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/* wait for clock acquisition */
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usleep_range (1000 , 1500 );
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@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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err_clk_ref :
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clk_disable_unprepare (res -> aux_clk );
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err_clk_aux :
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- clk_disable_unprepare (res -> phy_clk );
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- err_clk_phy :
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clk_disable_unprepare (res -> core_clk );
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err_clk_core :
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clk_disable_unprepare (res -> iface_clk );
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