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MIPS: Implement microMIPS MT ASE helpers
Implement various microMIPS MT ASE helpers accroading to: MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Fixes build error: {standard input}:2616: Error: branch to a symbol in another ISA mode This make MT ASE available on microMIPS as well. Boot tested on M5150 with microMIPS enabled on M5150. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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-112
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4 files changed

+179
-112
lines changed

‎arch/mips/include/asm/asmmacro.h

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -216,27 +216,33 @@
216216
* Temporary until all gas have MT ASE support
217217
*/
218218
.macro DMT reg=0
219-
.word 0x41600bc1 | (\reg << 16)
219+
insn_if_mips 0x41600bc1 | (\reg << 16)
220+
insn32_if_mm 0x0000057C | (\reg << 21)
220221
.endm
221222

222223
.macro EMT reg=0
223-
.word 0x41600be1 | (\reg << 16)
224+
insn_if_mips 0x41600be1 | (\reg << 16)
225+
insn32_if_mm 0x0000257C | (\reg << 21)
224226
.endm
225227

226228
.macro DVPE reg=0
227-
.word 0x41600001 | (\reg << 16)
229+
insn_if_mips 0x41600001 | (\reg << 16)
230+
insn32_if_mm 0x0000157C | (\reg << 21)
228231
.endm
229232

230233
.macro EVPE reg=0
231-
.word 0x41600021 | (\reg << 16)
234+
insn_if_mips 0x41600021 | (\reg << 16)
235+
insn32_if_mm 0x0000357C | (\reg << 21)
232236
.endm
233237

234-
.macro MFTR rt=0, rd=0, u=0, sel=0
235-
.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
238+
.macro MFTR rs=0, rt=0, u=0, sel=0
239+
insn_if_mips 0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
240+
insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
236241
.endm
237242

238-
.macro MTTR rt=0, rd=0, u=0, sel=0
239-
.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
243+
.macro MTTR rt=0, rs=0, u=0, sel=0
244+
insn_if_mips 0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
245+
insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
240246
.endm
241247

242248
#ifdef TOOLCHAIN_SUPPORTS_MSA

‎arch/mips/include/asm/mipsmtregs.h

Lines changed: 154 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -189,36 +189,47 @@ static inline unsigned core_nvpes(void)
189189
return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
190190
}
191191

192+
#define _ASM_SET_DVPE \
193+
_ASM_MACRO_1R(dvpe, rt, \
194+
_ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \
195+
_ASM_INSN32_IF_MM(0x0000157C | __rt << 21))
196+
#define _ASM_UNSET_DVPE ".purgem dvpe\n\t"
197+
192198
static inline unsigned int dvpe(void)
193199
{
194200
int res = 0;
195201

196202
__asm__ __volatile__(
197-
" .set push \n"
198-
" .set noreorder \n"
199-
" .set noat \n"
200-
" .set mips32r2 \n"
201-
" .word 0x41610001 # dvpe $1 \n"
202-
" move %0, $1 \n"
203-
" ehb \n"
204-
" .set pop \n"
203+
" .set push \n"
204+
" .set "MIPS_ISA_LEVEL" \n"
205+
_ASM_SET_DVPE
206+
" dvpe %0 \n"
207+
" ehb \n"
208+
_ASM_UNSET_DVPE
209+
" .set pop \n"
205210
: "=r" (res));
206211

207212
instruction_hazard();
208213

209214
return res;
210215
}
211216

217+
#define _ASM_SET_EVPE \
218+
_ASM_MACRO_1R(evpe, rt, \
219+
_ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \
220+
_ASM_INSN32_IF_MM(0x0000357C | __rt << 21))
221+
#define _ASM_UNSET_EVPE ".purgem evpe\n\t"
222+
212223
static inline void __raw_evpe(void)
213224
{
214225
__asm__ __volatile__(
215-
" .set push \n"
216-
" .set noreorder \n"
217-
" .set noat \n"
218-
" .set mips32r2 \n"
219-
" .word 0x41600021 # evpe \n"
220-
" ehb \n"
221-
" .set pop \n");
226+
" .set push \n"
227+
" .set "MIPS_ISA_LEVEL" \n"
228+
_ASM_SET_EVPE
229+
" evpe $0 \n"
230+
" ehb \n"
231+
_ASM_UNSET_EVPE
232+
" .set pop \n");
222233
}
223234

224235
/* Enable virtual processor execution if previous suggested it should be.
@@ -232,33 +243,46 @@ static inline void evpe(int previous)
232243
__raw_evpe();
233244
}
234245

246+
#define _ASM_SET_DMT \
247+
_ASM_MACRO_1R(dmt, rt, \
248+
_ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \
249+
_ASM_INSN32_IF_MM(0x0000057C | __rt << 21))
250+
#define _ASM_UNSET_DMT ".purgem dmt\n\t"
251+
235252
static inline unsigned int dmt(void)
236253
{
237254
int res;
238255

239256
__asm__ __volatile__(
240-
" .set push \n"
241-
" .set mips32r2 \n"
242-
" .set noat \n"
243-
" .word 0x41610BC1 # dmt $1 \n"
244-
" ehb \n"
245-
" move %0, $1 \n"
246-
" .set pop \n"
257+
" .set push \n"
258+
" .set "MIPS_ISA_LEVEL" \n"
259+
_ASM_SET_DMT
260+
" dmt %0 \n"
261+
" ehb \n"
262+
_ASM_UNSET_DMT
263+
" .set pop \n"
247264
: "=r" (res));
248265

249266
instruction_hazard();
250267

251268
return res;
252269
}
253270

271+
#define _ASM_SET_EMT \
272+
_ASM_MACRO_1R(emt, rt, \
273+
_ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \
274+
_ASM_INSN32_IF_MM(0x0000257C | __rt << 21))
275+
#define _ASM_UNSET_EMT ".purgem emt\n\t"
276+
254277
static inline void __raw_emt(void)
255278
{
256279
__asm__ __volatile__(
257-
" .set push \n"
258-
" .set noreorder \n"
259-
" .set mips32r2 \n"
260-
" .word 0x41600be1 # emt \n"
261-
" ehb \n"
280+
" .set push \n"
281+
" .set "MIPS_ISA_LEVEL" \n"
282+
_ASM_SET_EMT
283+
" emt $0 \n"
284+
_ASM_UNSET_EMT
285+
" ehb \n"
262286
" .set pop");
263287
}
264288

@@ -276,41 +300,55 @@ static inline void emt(int previous)
276300
static inline void ehb(void)
277301
{
278302
__asm__ __volatile__(
279-
" .set push \n"
280-
" .set mips32r2 \n"
281-
" ehb \n"
282-
" .set pop \n");
303+
" .set push \n"
304+
" .set "MIPS_ISA_LEVEL" \n"
305+
" ehb \n"
306+
" .set pop \n");
283307
}
284308

285-
#define mftc0(rt,sel) \
309+
#define _ASM_SET_MFTC0 \
310+
_ASM_MACRO_2R_1S(mftc0, rs, rt, sel, \
311+
_ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \
312+
__rs << 11 | \\sel) \
313+
_ASM_INSN32_IF_MM(0x0000000E | __rt << 21 | \
314+
__rs << 16 | \\sel << 4))
315+
#define _ASM_UNSET_MFTC0 ".purgem mftc0\n\t"
316+
317+
#define mftc0(rt, sel) \
286318
({ \
287-
unsigned long __res; \
319+
unsigned long __res; \
288320
\
289321
__asm__ __volatile__( \
290-
" .set push \n" \
291-
" .set mips32r2 \n" \
292-
" .set noat \n" \
293-
" # mftc0 $1, $" #rt ", " #sel " \n" \
294-
" .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
295-
" move %0, $1 \n" \
296-
" .set pop \n" \
322+
" .set push \n" \
323+
" .set "MIPS_ISA_LEVEL" \n" \
324+
_ASM_SET_MFTC0 \
325+
" mftc0 $1, " #rt ", " #sel " \n" \
326+
_ASM_UNSET_MFTC0 \
327+
" .set pop \n" \
297328
: "=r" (__res)); \
298329
\
299330
__res; \
300331
})
301332

333+
#define _ASM_SET_MFTGPR \
334+
_ASM_MACRO_2R(mftgpr, rs, rt, \
335+
_ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \
336+
__rs << 11) \
337+
_ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \
338+
__rs << 16))
339+
#define _ASM_UNSET_MFTGPR ".purgem mftgpr\n\t"
340+
302341
#define mftgpr(rt) \
303342
({ \
304343
unsigned long __res; \
305344
\
306345
__asm__ __volatile__( \
307-
" .set push \n" \
308-
" .set noat \n" \
309-
" .set mips32r2 \n" \
310-
" # mftgpr $1," #rt " \n" \
311-
" .word 0x41000820 | (" #rt " << 16) \n" \
312-
" move %0, $1 \n" \
313-
" .set pop \n" \
346+
" .set push \n" \
347+
" .set "MIPS_ISA_LEVEL" \n" \
348+
_ASM_SET_MFTGPR \
349+
" mftgpr %0," #rt " \n" \
350+
_ASM_UNSET_MFTGPR \
351+
" .set pop \n" \
314352
: "=r" (__res)); \
315353
\
316354
__res; \
@@ -321,35 +359,49 @@ static inline void ehb(void)
321359
unsigned long __res; \
322360
\
323361
__asm__ __volatile__( \
324-
" mftr %0, " #rt ", " #u ", " #sel " \n" \
362+
" mftr %0, " #rt ", " #u ", " #sel " \n" \
325363
: "=r" (__res)); \
326364
\
327365
__res; \
328366
})
329367

330-
#define mttgpr(rd,v) \
368+
#define _ASM_SET_MTTGPR \
369+
_ASM_MACRO_2R(mttgpr, rt, rs, \
370+
_ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \
371+
__rs << 11) \
372+
_ASM_INSN32_IF_MM(0x00000406 | __rt << 21 | \
373+
__rs << 16))
374+
#define _ASM_UNSET_MTTGPR ".purgem mttgpr\n\t"
375+
376+
#define mttgpr(rs, v) \
331377
do { \
332378
__asm__ __volatile__( \
333-
" .set push \n" \
334-
" .set mips32r2 \n" \
335-
" .set noat \n" \
336-
" move $1, %0 \n" \
337-
" # mttgpr $1, " #rd " \n" \
338-
" .word 0x41810020 | (" #rd " << 11) \n" \
339-
" .set pop \n" \
379+
" .set push \n" \
380+
" .set "MIPS_ISA_LEVEL" \n" \
381+
_ASM_SET_MTTGPR \
382+
" mttgpr %0, " #rs " \n" \
383+
_ASM_UNSET_MTTGPR \
384+
" .set pop \n" \
340385
: : "r" (v)); \
341386
} while (0)
342387

343-
#define mttc0(rd, sel, v) \
388+
#define _ASM_SET_MTTC0 \
389+
_ASM_MACRO_2R_1S(mttc0, rt, rs, sel, \
390+
_ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \
391+
__rs << 11 | \\sel) \
392+
_ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \
393+
__rs << 16 | \\sel << 4))
394+
#define _ASM_UNSET_MTTC0 ".purgem mttc0\n\t"
395+
396+
#define mttc0(rs, sel, v) \
344397
({ \
345398
__asm__ __volatile__( \
346-
" .set push \n" \
347-
" .set mips32r2 \n" \
348-
" .set noat \n" \
349-
" move $1, %0 \n" \
350-
" # mttc0 %0," #rd ", " #sel " \n" \
351-
" .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
352-
" .set pop \n" \
399+
" .set push \n" \
400+
" .set "MIPS_ISA_LEVEL" \n" \
401+
_ASM_SET_MTTC0 \
402+
" mttc0 %0," #rs ", " #sel " \n" \
403+
_ASM_UNSET_MTTC0 \
404+
" .set pop \n" \
353405
: \
354406
: "r" (v)); \
355407
})
@@ -371,49 +423,49 @@ do { \
371423

372424

373425
/* you *must* set the target tc (settc) before trying to use these */
374-
#define read_vpe_c0_vpecontrol() mftc0(1, 1)
375-
#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
376-
#define read_vpe_c0_vpeconf0() mftc0(1, 2)
377-
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
378-
#define read_vpe_c0_vpeconf1() mftc0(1, 3)
379-
#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
380-
#define read_vpe_c0_count() mftc0(9, 0)
381-
#define write_vpe_c0_count(val) mttc0(9, 0, val)
382-
#define read_vpe_c0_status() mftc0(12, 0)
383-
#define write_vpe_c0_status(val) mttc0(12, 0, val)
384-
#define read_vpe_c0_cause() mftc0(13, 0)
385-
#define write_vpe_c0_cause(val) mttc0(13, 0, val)
386-
#define read_vpe_c0_config() mftc0(16, 0)
387-
#define write_vpe_c0_config(val) mttc0(16, 0, val)
388-
#define read_vpe_c0_config1() mftc0(16, 1)
389-
#define write_vpe_c0_config1(val) mttc0(16, 1, val)
390-
#define read_vpe_c0_config7() mftc0(16, 7)
391-
#define write_vpe_c0_config7(val) mttc0(16, 7, val)
392-
#define read_vpe_c0_ebase() mftc0(15, 1)
393-
#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
394-
#define write_vpe_c0_compare(val) mttc0(11, 0, val)
395-
#define read_vpe_c0_badvaddr() mftc0(8, 0)
396-
#define read_vpe_c0_epc() mftc0(14, 0)
397-
#define write_vpe_c0_epc(val) mttc0(14, 0, val)
426+
#define read_vpe_c0_vpecontrol() mftc0($1, 1)
427+
#define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val)
428+
#define read_vpe_c0_vpeconf0() mftc0($1, 2)
429+
#define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val)
430+
#define read_vpe_c0_vpeconf1() mftc0($1, 3)
431+
#define write_vpe_c0_vpeconf1(val) mttc0($1, 3, val)
432+
#define read_vpe_c0_count() mftc0($9, 0)
433+
#define write_vpe_c0_count(val) mttc0($9, 0, val)
434+
#define read_vpe_c0_status() mftc0($12, 0)
435+
#define write_vpe_c0_status(val) mttc0($12, 0, val)
436+
#define read_vpe_c0_cause() mftc0($13, 0)
437+
#define write_vpe_c0_cause(val) mttc0($13, 0, val)
438+
#define read_vpe_c0_config() mftc0($16, 0)
439+
#define write_vpe_c0_config(val) mttc0($16, 0, val)
440+
#define read_vpe_c0_config1() mftc0($16, 1)
441+
#define write_vpe_c0_config1(val) mttc0($16, 1, val)
442+
#define read_vpe_c0_config7() mftc0($16, 7)
443+
#define write_vpe_c0_config7(val) mttc0($16, 7, val)
444+
#define read_vpe_c0_ebase() mftc0($15, 1)
445+
#define write_vpe_c0_ebase(val) mttc0($15, 1, val)
446+
#define write_vpe_c0_compare(val) mttc0($11, 0, val)
447+
#define read_vpe_c0_badvaddr() mftc0($8, 0)
448+
#define read_vpe_c0_epc() mftc0($14, 0)
449+
#define write_vpe_c0_epc(val) mttc0($14, 0, val)
398450

399451

400452
/* TC */
401-
#define read_tc_c0_tcstatus() mftc0(2, 1)
402-
#define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
403-
#define read_tc_c0_tcbind() mftc0(2, 2)
404-
#define write_tc_c0_tcbind(val) mttc0(2, 2, val)
405-
#define read_tc_c0_tcrestart() mftc0(2, 3)
406-
#define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
407-
#define read_tc_c0_tchalt() mftc0(2, 4)
408-
#define write_tc_c0_tchalt(val) mttc0(2, 4, val)
409-
#define read_tc_c0_tccontext() mftc0(2, 5)
410-
#define write_tc_c0_tccontext(val) mttc0(2, 5, val)
453+
#define read_tc_c0_tcstatus() mftc0($2, 1)
454+
#define write_tc_c0_tcstatus(val) mttc0($2, 1, val)
455+
#define read_tc_c0_tcbind() mftc0($2, 2)
456+
#define write_tc_c0_tcbind(val) mttc0($2, 2, val)
457+
#define read_tc_c0_tcrestart() mftc0($2, 3)
458+
#define write_tc_c0_tcrestart(val) mttc0($2, 3, val)
459+
#define read_tc_c0_tchalt() mftc0($2, 4)
460+
#define write_tc_c0_tchalt(val) mttc0($2, 4, val)
461+
#define read_tc_c0_tccontext() mftc0($2, 5)
462+
#define write_tc_c0_tccontext(val) mttc0($2, 5, val)
411463

412464
/* GPR */
413-
#define read_tc_gpr_sp() mftgpr(29)
414-
#define write_tc_gpr_sp(val) mttgpr(29, val)
415-
#define read_tc_gpr_gp() mftgpr(28)
416-
#define write_tc_gpr_gp(val) mttgpr(28, val)
465+
#define read_tc_gpr_sp() mftgpr($29)
466+
#define write_tc_gpr_sp(val) mttgpr($29, val)
467+
#define read_tc_gpr_gp() mftgpr($28)
468+
#define write_tc_gpr_gp(val) mttgpr($28, val)
417469

418470
__BUILD_SET_C0(mvpcontrol)
419471

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