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claudiubezneageertu
claudiubeznea
authored and
geertu
committed
clk: renesas: Add minimal boot support for RZ/G3S SoC
Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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-1
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5 files changed

+228
-1
lines changed

‎drivers/clk/renesas/Kconfig

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ config CLK_RENESAS
3737
select CLK_R9A07G043 if ARCH_R9A07G043
3838
select CLK_R9A07G044 if ARCH_R9A07G044
3939
select CLK_R9A07G054 if ARCH_R9A07G054
40+
select CLK_R9A08G045 if ARCH_R9A08G045
4041
select CLK_R9A09G011 if ARCH_R9A09G011
4142
select CLK_SH73A0 if ARCH_SH73A0
4243

@@ -179,6 +180,10 @@ config CLK_R9A07G054
179180
bool "RZ/V2L clock support" if COMPILE_TEST
180181
select CLK_RZG2L
181182

183+
config CLK_R9A08G045
184+
bool "RZ/G3S clock support" if COMPILE_TEST
185+
select CLK_RZG2L
186+
182187
config CLK_R9A09G011
183188
bool "RZ/V2M clock support" if COMPILE_TEST
184189
select CLK_RZG2L
@@ -215,7 +220,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
215220
This is a driver for R-Car USB2 clock selector
216221

217222
config CLK_RZG2L
218-
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
223+
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
219224
select RESET_CONTROLLER
220225

221226
# Generic

‎drivers/clk/renesas/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3434
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3535
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3636
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
37+
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
3738
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
3839
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
3940

‎drivers/clk/renesas/r9a08g045-cpg.c

Lines changed: 214 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,214 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* RZ/G3S CPG driver
4+
*
5+
* Copyright (C) 2023 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/r9a08g045-cpg.h>
14+
15+
#include "rzg2l-cpg.h"
16+
17+
/* RZ/G3S Specific registers. */
18+
#define G3S_CPG_PL2_DDIV (0x204)
19+
#define G3S_CPG_SDHI_DDIV (0x218)
20+
#define G3S_CPG_PLL_DSEL (0x240)
21+
#define G3S_CPG_SDHI_DSEL (0x244)
22+
#define G3S_CLKDIVSTATUS (0x280)
23+
#define G3S_CLKSELSTATUS (0x284)
24+
25+
/* RZ/G3S Specific division configuration. */
26+
#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3)
27+
#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
28+
29+
/* RZ/G3S Clock status configuration. */
30+
#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
31+
#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1)
32+
#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1)
33+
#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1)
34+
#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1)
35+
#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1)
36+
37+
#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1)
38+
#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1)
39+
40+
/* RZ/G3S Specific clocks select. */
41+
#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1)
42+
#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
43+
44+
/* PLL 1/4/6 configuration registers macro. */
45+
#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
46+
47+
#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
48+
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
49+
.parent_names = (_parent_names), \
50+
.num_parents = ARRAY_SIZE((_parent_names)), \
51+
.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
52+
.flag = (_clk_flags))
53+
54+
enum clk_ids {
55+
/* Core Clock Outputs exported to DT */
56+
LAST_DT_CORE_CLK = R9A08G045_SWD,
57+
58+
/* External Input Clocks */
59+
CLK_EXTAL,
60+
61+
/* Internal Core Clocks */
62+
CLK_OSC_DIV1000,
63+
CLK_PLL1,
64+
CLK_PLL2,
65+
CLK_PLL2_DIV2,
66+
CLK_PLL2_DIV2_8,
67+
CLK_PLL2_DIV6,
68+
CLK_PLL3,
69+
CLK_PLL3_DIV2,
70+
CLK_PLL3_DIV2_4,
71+
CLK_PLL3_DIV2_8,
72+
CLK_PLL3_DIV6,
73+
CLK_PLL4,
74+
CLK_PLL6,
75+
CLK_PLL6_DIV2,
76+
CLK_SEL_SDHI0,
77+
CLK_SEL_PLL4,
78+
CLK_P1_DIV2,
79+
CLK_P3_DIV2,
80+
CLK_SD0_DIV4,
81+
82+
/* Module Clocks */
83+
MOD_CLK_BASE,
84+
};
85+
86+
/* Divider tables */
87+
static const struct clk_div_table dtable_1_2[] = {
88+
{ 0, 1 },
89+
{ 1, 2 },
90+
{ 0, 0 },
91+
};
92+
93+
static const struct clk_div_table dtable_1_8[] = {
94+
{ 0, 1 },
95+
{ 1, 2 },
96+
{ 2, 4 },
97+
{ 3, 8 },
98+
{ 0, 0 },
99+
};
100+
101+
static const struct clk_div_table dtable_1_32[] = {
102+
{ 0, 1 },
103+
{ 1, 2 },
104+
{ 2, 4 },
105+
{ 3, 8 },
106+
{ 4, 32 },
107+
{ 0, 0 },
108+
};
109+
110+
/* Mux clock names tables. */
111+
static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" };
112+
static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" };
113+
114+
/* Mux clock indices tables. */
115+
static const u32 mtable_sd[] = { 0, 2, 3 };
116+
static const u32 mtable_pll4[] = { 0, 1 };
117+
118+
static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
119+
/* External Clock Inputs */
120+
DEF_INPUT("extal", CLK_EXTAL),
121+
122+
/* Internal Core Clocks */
123+
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
124+
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
125+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
126+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
127+
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
128+
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
129+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
130+
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
131+
DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
132+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
133+
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
134+
DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8),
135+
DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6),
136+
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2),
137+
DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi,
138+
mtable_sd, 0, NULL),
139+
DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4,
140+
mtable_pll4, CLK_SET_PARENT_GATE, NULL),
141+
142+
/* Core output clk */
143+
DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
144+
0, 0, 0, NULL),
145+
DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS,
146+
dtable_1_32, 0, 0, 0, NULL),
147+
DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS,
148+
dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
149+
rzg3s_cpg_div_clk_notifier),
150+
DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4),
151+
DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
152+
DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS,
153+
dtable_1_32, 0, 0, 0, NULL),
154+
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2),
155+
DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS,
156+
dtable_1_32, 0, 0, 0, NULL),
157+
DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
158+
dtable_1_32, 0, 0, 0, NULL),
159+
DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
160+
DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
161+
DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
162+
DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
163+
};
164+
165+
static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
166+
DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
167+
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
168+
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
169+
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
170+
DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
171+
DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
172+
DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
173+
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
174+
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
175+
};
176+
177+
static const struct rzg2l_reset r9a08g045_resets[] = {
178+
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
179+
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
180+
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
181+
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
182+
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
183+
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
184+
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
185+
};
186+
187+
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
188+
MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
189+
MOD_CLK_BASE + R9A08G045_IA55_CLK,
190+
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
191+
};
192+
193+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
194+
/* Core Clocks */
195+
.core_clks = r9a08g045_core_clks,
196+
.num_core_clks = ARRAY_SIZE(r9a08g045_core_clks),
197+
.last_dt_core_clk = LAST_DT_CORE_CLK,
198+
.num_total_core_clks = MOD_CLK_BASE,
199+
200+
/* Critical Module Clocks */
201+
.crit_mod_clks = r9a08g045_crit_mod_clks,
202+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks),
203+
204+
/* Module Clocks */
205+
.mod_clks = r9a08g045_mod_clks,
206+
.num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
207+
.num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
208+
209+
/* Resets */
210+
.resets = r9a08g045_resets,
211+
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
212+
213+
.has_clk_mon_regs = true,
214+
};

‎drivers/clk/renesas/rzg2l-cpg.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1706,6 +1706,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
17061706
.data = &r9a07g054_cpg_info,
17071707
},
17081708
#endif
1709+
#ifdef CONFIG_CLK_R9A08G045
1710+
{
1711+
.compatible = "renesas,r9a08g045-cpg",
1712+
.data = &r9a08g045_cpg_info,
1713+
},
1714+
#endif
17091715
#ifdef CONFIG_CLK_R9A09G011
17101716
{
17111717
.compatible = "renesas,r9a09g011-cpg",

‎drivers/clk/renesas/rzg2l-cpg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -284,6 +284,7 @@ struct rzg2l_cpg_info {
284284
extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
285285
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
286286
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
287+
extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
287288
extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
288289

289290
int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);

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