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Merge tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux into for-next/fixes
coresight: trbe: Workaround Cortex-A510 erratas This pull request is providing arm64 definitions to support TRBE Cortex-A510 erratas. Signed-off-by: Mathieu Poirier <[email protected]> * tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux: arm64: errata: Add detection for TRBE trace data corruption arm64: errata: Add detection for TRBE invalid prohibited states arm64: errata: Add detection for TRBE ignored system register writes arm64: Add Cortex-A510 CPU part definition
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‎Documentation/arm64/silicon-errata.rst

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@@ -52,6 +52,12 @@ stable kernels.
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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |

‎arch/arm64/Kconfig

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@@ -778,6 +778,65 @@ config ARM64_ERRATUM_2224489
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If unsure, say Y.
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config ARM64_ERRATUM_2064142
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bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 2064142.
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Affected Cortex-A510 core might fail to write into system registers after the
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TRBE has been disabled. Under some conditions after the TRBE has been disabled
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writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
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and TRBTRG_EL1 will be ignored and will not be effected.
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Work around this in the driver by executing TSB CSYNC and DSB after collection
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is stopped and before performing a system register write to one of the affected
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registers.
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If unsure, say Y.
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config ARM64_ERRATUM_2038923
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bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 2038923.
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Affected Cortex-A510 core might cause an inconsistent view on whether trace is
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prohibited within the CPU. As a result, the trace buffer or trace buffer state
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might be corrupted. This happens after TRBE buffer has been enabled by setting
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TRBLIMITR_EL1.E, followed by just a single context synchronization event before
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execution changes from a context, in which trace is prohibited to one where it
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isn't, or vice versa. In these mentioned conditions, the view of whether trace
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is prohibited is inconsistent between parts of the CPU, and the trace buffer or
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the trace buffer state might be corrupted.
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Work around this in the driver by preventing an inconsistent view of whether the
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trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
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change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
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two ISB instructions if no ERET is to take place.
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If unsure, say Y.
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config ARM64_ERRATUM_1902691
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bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
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depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
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default y
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help
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This option adds the workaround for ARM Cortex-A510 erratum 1902691.
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Affected Cortex-A510 core might cause trace data corruption, when being written
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into the memory. Effectively TRBE is broken and hence cannot be used to capture
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trace data.
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Work around this problem in the driver by just preventing TRBE initialization on
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affected cpus. The firmware must have disabled the access to TRBE for the kernel
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on such implementations. This will cover the kernel for any firmware that doesn't
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do this already.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y

‎arch/arm64/include/asm/cputype.h

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@@ -73,6 +73,7 @@
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define ARM_CPU_PART_CORTEX_A77 0xD0D
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#define ARM_CPU_PART_CORTEX_A510 0xD46
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#define ARM_CPU_PART_CORTEX_A710 0xD47
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#define ARM_CPU_PART_CORTEX_X2 0xD48
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
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#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
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#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
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#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

‎arch/arm64/kernel/cpu_errata.c

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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2064142
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{
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.desc = "ARM erratum 2064142",
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.capability = ARM64_WORKAROUND_2064142,
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/* Cortex-A510 r0p0 - r0p2 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2038923
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{
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.desc = "ARM erratum 2038923",
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.capability = ARM64_WORKAROUND_2038923,
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/* Cortex-A510 r0p0 - r0p2 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1902691
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{
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.desc = "ARM erratum 1902691",
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.capability = ARM64_WORKAROUND_1902691,
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/* Cortex-A510 r0p0 - r0p1 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
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},
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#endif
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{
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}

‎arch/arm64/tools/cpucaps

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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_2064142
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WORKAROUND_2038923
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WORKAROUND_1902691
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

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