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mripardbebarino
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clk: bcm: rpi: Use CCF boundaries instead of rolling our own
The raspberrypi firmware clock driver has a min_rate / max_rate clamping by storing the info it needs in a private structure. However, the CCF already provides such a facility, so we can switch to it to remove the boilerplate. Reviewed-by: Nicolas Saenz Julienne <[email protected]> Tested-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/d4c53dab6de5d5f70743d9c139d0117589530e62.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <[email protected]>
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drivers/clk/bcm/clk-raspberrypi.c

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,6 @@ struct raspberrypi_clk {
3636
struct rpi_firmware *firmware;
3737
struct platform_device *cpufreq;
3838

39-
unsigned long min_rate;
40-
unsigned long max_rate;
41-
4239
struct clk_hw pllb;
4340
};
4441

@@ -142,13 +139,11 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
142139
static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
143140
struct clk_rate_request *req)
144141
{
145-
struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
146-
pllb);
147142
u64 div, final_rate;
148143
u32 ndiv, fdiv;
149144

150145
/* We can't use req->rate directly as it would overflow */
151-
final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
146+
final_rate = clamp(req->rate, req->min_rate, req->max_rate);
152147

153148
div = (u64)final_rate << A2W_PLL_FRAC_BITS;
154149
do_div(div, req->best_parent_rate);
@@ -215,12 +210,15 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
215210
dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
216211
min_rate, max_rate);
217212

218-
rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
219-
rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
220-
221213
rpi->pllb.init = &init;
222214

223-
return devm_clk_hw_register(rpi->dev, &rpi->pllb);
215+
ret = devm_clk_hw_register(rpi->dev, &rpi->pllb);
216+
if (!ret)
217+
clk_hw_set_rate_range(&rpi->pllb,
218+
min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
219+
max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
220+
221+
return ret;
224222
}
225223

226224
static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {

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