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Merge tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet: - Update audio clock gate hierarchy for meson8 and gxbb - Update g12a spicc clock sources * tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate
2 parents bb6d3fb + 71202c4 commit dfbfee8

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7 files changed

+164
-18
lines changed

7 files changed

+164
-18
lines changed

‎drivers/clk/meson/g12a.c

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = {
38623862
},
38633863
};
38643864

3865+
/* SPICC SCLK source clock */
3866+
3867+
static const struct clk_parent_data spicc_sclk_parent_data[] = {
3868+
{ .fw_name = "xtal", },
3869+
{ .hw = &g12a_clk81.hw },
3870+
{ .hw = &g12a_fclk_div4.hw },
3871+
{ .hw = &g12a_fclk_div3.hw },
3872+
{ .hw = &g12a_fclk_div5.hw },
3873+
{ .hw = &g12a_fclk_div7.hw },
3874+
};
3875+
3876+
static struct clk_regmap g12a_spicc0_sclk_sel = {
3877+
.data = &(struct clk_regmap_mux_data){
3878+
.offset = HHI_SPICC_CLK_CNTL,
3879+
.mask = 7,
3880+
.shift = 7,
3881+
},
3882+
.hw.init = &(struct clk_init_data){
3883+
.name = "spicc0_sclk_sel",
3884+
.ops = &clk_regmap_mux_ops,
3885+
.parent_data = spicc_sclk_parent_data,
3886+
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3887+
},
3888+
};
3889+
3890+
static struct clk_regmap g12a_spicc0_sclk_div = {
3891+
.data = &(struct clk_regmap_div_data){
3892+
.offset = HHI_SPICC_CLK_CNTL,
3893+
.shift = 0,
3894+
.width = 6,
3895+
},
3896+
.hw.init = &(struct clk_init_data){
3897+
.name = "spicc0_sclk_div",
3898+
.ops = &clk_regmap_divider_ops,
3899+
.parent_hws = (const struct clk_hw *[]) {
3900+
&g12a_spicc0_sclk_sel.hw
3901+
},
3902+
.num_parents = 1,
3903+
.flags = CLK_SET_RATE_PARENT,
3904+
},
3905+
};
3906+
3907+
static struct clk_regmap g12a_spicc0_sclk = {
3908+
.data = &(struct clk_regmap_gate_data){
3909+
.offset = HHI_SPICC_CLK_CNTL,
3910+
.bit_idx = 6,
3911+
},
3912+
.hw.init = &(struct clk_init_data){
3913+
.name = "spicc0_sclk",
3914+
.ops = &clk_regmap_gate_ops,
3915+
.parent_hws = (const struct clk_hw *[]) {
3916+
&g12a_spicc0_sclk_div.hw
3917+
},
3918+
.num_parents = 1,
3919+
.flags = CLK_SET_RATE_PARENT,
3920+
},
3921+
};
3922+
3923+
static struct clk_regmap g12a_spicc1_sclk_sel = {
3924+
.data = &(struct clk_regmap_mux_data){
3925+
.offset = HHI_SPICC_CLK_CNTL,
3926+
.mask = 7,
3927+
.shift = 23,
3928+
},
3929+
.hw.init = &(struct clk_init_data){
3930+
.name = "spicc1_sclk_sel",
3931+
.ops = &clk_regmap_mux_ops,
3932+
.parent_data = spicc_sclk_parent_data,
3933+
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
3934+
},
3935+
};
3936+
3937+
static struct clk_regmap g12a_spicc1_sclk_div = {
3938+
.data = &(struct clk_regmap_div_data){
3939+
.offset = HHI_SPICC_CLK_CNTL,
3940+
.shift = 16,
3941+
.width = 6,
3942+
},
3943+
.hw.init = &(struct clk_init_data){
3944+
.name = "spicc1_sclk_div",
3945+
.ops = &clk_regmap_divider_ops,
3946+
.parent_hws = (const struct clk_hw *[]) {
3947+
&g12a_spicc1_sclk_sel.hw
3948+
},
3949+
.num_parents = 1,
3950+
.flags = CLK_SET_RATE_PARENT,
3951+
},
3952+
};
3953+
3954+
static struct clk_regmap g12a_spicc1_sclk = {
3955+
.data = &(struct clk_regmap_gate_data){
3956+
.offset = HHI_SPICC_CLK_CNTL,
3957+
.bit_idx = 22,
3958+
},
3959+
.hw.init = &(struct clk_init_data){
3960+
.name = "spicc1_sclk",
3961+
.ops = &clk_regmap_gate_ops,
3962+
.parent_hws = (const struct clk_hw *[]) {
3963+
&g12a_spicc1_sclk_div.hw
3964+
},
3965+
.num_parents = 1,
3966+
.flags = CLK_SET_RATE_PARENT,
3967+
},
3968+
};
3969+
38653970
#define MESON_GATE(_name, _reg, _bit) \
38663971
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
38673972

@@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
41594264
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
41604265
[CLKID_TS_DIV] = &g12a_ts_div.hw,
41614266
[CLKID_TS] = &g12a_ts.hw,
4267+
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4268+
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4269+
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4270+
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4271+
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4272+
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
41624273
[NR_CLKS] = NULL,
41634274
},
41644275
.num = NR_CLKS,
@@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
44084519
[CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
44094520
[CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
44104521
[CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4522+
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4523+
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4524+
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4525+
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4526+
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4527+
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
44114528
[NR_CLKS] = NULL,
44124529
},
44134530
.num = NR_CLKS,
@@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
46424759
[CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
46434760
[CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
46444761
[CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4762+
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4763+
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4764+
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4765+
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4766+
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4767+
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
46454768
[NR_CLKS] = NULL,
46464769
},
46474770
.num = NR_CLKS,
@@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
48775000
&sm1_cpu1_clk,
48785001
&sm1_cpu2_clk,
48795002
&sm1_cpu3_clk,
5003+
&g12a_spicc0_sclk_sel,
5004+
&g12a_spicc0_sclk_div,
5005+
&g12a_spicc0_sclk,
5006+
&g12a_spicc1_sclk_sel,
5007+
&g12a_spicc1_sclk_div,
5008+
&g12a_spicc1_sclk,
48805009
};
48815010

48825011
static const struct reg_sequence g12a_init_regs[] = {

‎drivers/clk/meson/g12a.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,8 +255,12 @@
255255
#define CLKID_DSU_CLK_DYN1 249
256256
#define CLKID_DSU_CLK_DYN 250
257257
#define CLKID_DSU_CLK_FINAL 251
258+
#define CLKID_SPICC0_SCLK_SEL 256
259+
#define CLKID_SPICC0_SCLK_DIV 257
260+
#define CLKID_SPICC1_SCLK_SEL 259
261+
#define CLKID_SPICC1_SCLK_DIV 260
258262

259-
#define NR_CLKS 256
263+
#define NR_CLKS 262
260264

261265
/* include the CLKIDs that have been made part of the DT binding */
262266
#include <dt-bindings/clock/g12a-clkc.h>

‎drivers/clk/meson/gxbb.c

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2613,19 +2613,12 @@ static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
26132613
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
26142614
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
26152615
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2616+
static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
26162617
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
26172618

26182619
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
26192620
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
26202621
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2621-
static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
2622-
static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
2623-
static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
2624-
static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
2625-
static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
2626-
static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
2627-
static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
2628-
static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
26292622
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
26302623
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
26312624
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
@@ -2680,6 +2673,16 @@ static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
26802673
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
26812674
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
26822675

2676+
/* AIU gates */
2677+
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2678+
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2679+
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2680+
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2681+
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2682+
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2683+
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2684+
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2685+
26832686
/* Array of all clocks provided by this provider */
26842687

26852688
static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
@@ -3100,6 +3103,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
31003103
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
31013104
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
31023105
[CLKID_HDMI] = &gxbb_hdmi.hw,
3106+
[CLKID_ACODEC] = &gxl_acodec.hw,
31033107
[NR_CLKS] = NULL,
31043108
},
31053109
.num = NR_CLKS,
@@ -3491,6 +3495,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
34913495
&gxl_hdmi_pll_od,
34923496
&gxl_hdmi_pll_od2,
34933497
&gxl_hdmi_pll_dco,
3498+
&gxl_acodec,
34943499
};
34953500

34963501
static const struct meson_eeclkc_data gxbb_clkc_data = {

‎drivers/clk/meson/gxbb.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,7 @@
188188
#define CLKID_HDMI_SEL 203
189189
#define CLKID_HDMI_DIV 204
190190

191-
#define NR_CLKS 206
191+
#define NR_CLKS 207
192192

193193
/* include the CLKIDs that have been made part of the DT binding */
194194
#include <dt-bindings/clock/gxbb-clkc.h>

‎drivers/clk/meson/meson8b.c

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2605,14 +2605,6 @@ static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
26052605
static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
26062606
static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
26072607
static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2608-
static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
2609-
static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2610-
static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2611-
static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2612-
static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2613-
static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2614-
static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2615-
static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
26162608
static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
26172609
static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
26182610
static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
@@ -2659,6 +2651,19 @@ static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
26592651
static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
26602652
static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
26612653

2654+
/* AIU gates */
2655+
#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2656+
MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2657+
2658+
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2659+
static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2660+
static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2661+
static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2662+
static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2663+
static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2664+
static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2665+
static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2666+
26622667
/* Always On (AO) domain gates */
26632668

26642669
static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);

‎include/dt-bindings/clock/g12a-clkc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,5 +143,7 @@
143143
#define CLKID_CPU1_CLK 253
144144
#define CLKID_CPU2_CLK 254
145145
#define CLKID_CPU3_CLK 255
146+
#define CLKID_SPICC0_SCLK 258
147+
#define CLKID_SPICC1_SCLK 261
146148

147149
#endif /* __G12A_CLKC_H */

‎include/dt-bindings/clock/gxbb-clkc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,5 +146,6 @@
146146
#define CLKID_CTS_VDAC 201
147147
#define CLKID_HDMI_TX 202
148148
#define CLKID_HDMI 205
149+
#define CLKID_ACODEC 206
149150

150151
#endif /* __GXBB_CLKC_H */

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