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perf vendor events intel: Update meteorlake to 1.03
1.03 events were released in: intel/perfmon@501a29e It added a lot of events and all uncore events. Signed-off-by: Ian Rogers <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Eduard Zingerman <[email protected]> Cc: Sohom Datta <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Adrian Hunter <[email protected]> Cc: Caleb Biggers <[email protected]> Cc: Edward Baker <[email protected]> Cc: Perry Taylor <[email protected]> Cc: Samantha Alt <[email protected]> Cc: Weilin Wang <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Andrii Nakryiko <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Jing Zhang <[email protected]> Cc: Kajol Jain <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Kan Liang <[email protected]> Cc: Zhengjun Xing <[email protected]> Cc: John Garry <[email protected]> Cc: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Namhyung Kim <[email protected]>
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‎tools/perf/pmu-events/arch/x86/mapfile.csv

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@@ -19,7 +19,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
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GenuineIntel-6-3E,v23,ivytown,core
2020
GenuineIntel-6-2D,v23,jaketown,core
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GenuineIntel-6-(57|85),v10,knightslanding,core
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GenuineIntel-6-A[AC],v1.01,meteorlake,core
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GenuineIntel-6-A[AC],v1.03,meteorlake,core
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GenuineIntel-6-1[AEF],v3,nehalemep,core
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GenuineIntel-6-2E,v3,nehalemex,core
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GenuineIntel-6-A7,v1.01,rocketlake,core

‎tools/perf/pmu-events/arch/x86/meteorlake/cache.json

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‎tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json

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[
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{
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"BriefDescription": "This event counts the cycles the floating point divider is busy.",
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"CounterMask": "1",
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"EventCode": "0xb0",
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"EventName": "ARITH.FPDIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts all microcode FP assists.",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.FP",
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"PublicDescription": "Counts all microcode Floating Point assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "ASSISTS.SSE_AVX_MIX",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.SSE_AVX_MIX",
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"SampleAfterValue": "1000003",
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"UMask": "0x10",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x10",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x20",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x18",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0x3",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
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"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0xfc",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
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"EventCode": "0xc3",
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"EventName": "MACHINE_CLEARS.FP_ASSIST",
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"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
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"SampleAfterValue": "20003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
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"EventCode": "0xc2",
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"EventName": "UOPS_RETIRED.FPDIV",
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"PEBS": "1",
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"SampleAfterValue": "2000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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}
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]

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