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LoongArch: KVM: Add vcpu related header files
Add LoongArch vcpu related header files, including vcpu csr information, irq number definitions, and some vcpu interfaces. Reviewed-by: Bibo Mao <[email protected]> Tested-by: Huacai Chen <[email protected]> Signed-off-by: Tianrui Zhao <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/kvm_csr.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_LOONGARCH_KVM_CSR_H__
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#define __ASM_LOONGARCH_KVM_CSR_H__
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#include <linux/uaccess.h>
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#include <linux/kvm_host.h>
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#include <asm/loongarch.h>
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#include <asm/kvm_vcpu.h>
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#define gcsr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__( \
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" gcsrrd %[val], %[reg]\n\t" \
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: [val] "=r" (__v) \
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: [reg] "i" (csr) \
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: "memory"); \
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__v; \
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})
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#define gcsr_write(v, csr) \
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({ \
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register unsigned long __v = v; \
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__asm__ __volatile__ ( \
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" gcsrwr %[val], %[reg]\n\t" \
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: [val] "+r" (__v) \
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: [reg] "i" (csr) \
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: "memory"); \
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})
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#define gcsr_xchg(v, m, csr) \
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({ \
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register unsigned long __v = v; \
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__asm__ __volatile__( \
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" gcsrxchg %[val], %[mask], %[reg]\n\t" \
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: [val] "+r" (__v) \
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: [mask] "r" (m), [reg] "i" (csr) \
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: "memory"); \
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__v; \
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})
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/* Guest CSRS read and write */
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#define read_gcsr_crmd() gcsr_read(LOONGARCH_CSR_CRMD)
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#define write_gcsr_crmd(val) gcsr_write(val, LOONGARCH_CSR_CRMD)
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#define read_gcsr_prmd() gcsr_read(LOONGARCH_CSR_PRMD)
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#define write_gcsr_prmd(val) gcsr_write(val, LOONGARCH_CSR_PRMD)
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#define read_gcsr_euen() gcsr_read(LOONGARCH_CSR_EUEN)
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#define write_gcsr_euen(val) gcsr_write(val, LOONGARCH_CSR_EUEN)
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#define read_gcsr_misc() gcsr_read(LOONGARCH_CSR_MISC)
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#define write_gcsr_misc(val) gcsr_write(val, LOONGARCH_CSR_MISC)
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#define read_gcsr_ecfg() gcsr_read(LOONGARCH_CSR_ECFG)
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#define write_gcsr_ecfg(val) gcsr_write(val, LOONGARCH_CSR_ECFG)
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#define read_gcsr_estat() gcsr_read(LOONGARCH_CSR_ESTAT)
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#define write_gcsr_estat(val) gcsr_write(val, LOONGARCH_CSR_ESTAT)
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#define read_gcsr_era() gcsr_read(LOONGARCH_CSR_ERA)
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#define write_gcsr_era(val) gcsr_write(val, LOONGARCH_CSR_ERA)
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#define read_gcsr_badv() gcsr_read(LOONGARCH_CSR_BADV)
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#define write_gcsr_badv(val) gcsr_write(val, LOONGARCH_CSR_BADV)
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#define read_gcsr_badi() gcsr_read(LOONGARCH_CSR_BADI)
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#define write_gcsr_badi(val) gcsr_write(val, LOONGARCH_CSR_BADI)
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#define read_gcsr_eentry() gcsr_read(LOONGARCH_CSR_EENTRY)
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#define write_gcsr_eentry(val) gcsr_write(val, LOONGARCH_CSR_EENTRY)
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#define read_gcsr_asid() gcsr_read(LOONGARCH_CSR_ASID)
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#define write_gcsr_asid(val) gcsr_write(val, LOONGARCH_CSR_ASID)
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#define read_gcsr_pgdl() gcsr_read(LOONGARCH_CSR_PGDL)
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#define write_gcsr_pgdl(val) gcsr_write(val, LOONGARCH_CSR_PGDL)
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#define read_gcsr_pgdh() gcsr_read(LOONGARCH_CSR_PGDH)
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#define write_gcsr_pgdh(val) gcsr_write(val, LOONGARCH_CSR_PGDH)
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#define write_gcsr_pgd(val) gcsr_write(val, LOONGARCH_CSR_PGD)
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#define read_gcsr_pgd() gcsr_read(LOONGARCH_CSR_PGD)
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#define read_gcsr_pwctl0() gcsr_read(LOONGARCH_CSR_PWCTL0)
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#define write_gcsr_pwctl0(val) gcsr_write(val, LOONGARCH_CSR_PWCTL0)
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#define read_gcsr_pwctl1() gcsr_read(LOONGARCH_CSR_PWCTL1)
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#define write_gcsr_pwctl1(val) gcsr_write(val, LOONGARCH_CSR_PWCTL1)
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#define read_gcsr_stlbpgsize() gcsr_read(LOONGARCH_CSR_STLBPGSIZE)
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#define write_gcsr_stlbpgsize(val) gcsr_write(val, LOONGARCH_CSR_STLBPGSIZE)
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#define read_gcsr_rvacfg() gcsr_read(LOONGARCH_CSR_RVACFG)
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#define write_gcsr_rvacfg(val) gcsr_write(val, LOONGARCH_CSR_RVACFG)
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#define read_gcsr_cpuid() gcsr_read(LOONGARCH_CSR_CPUID)
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#define write_gcsr_cpuid(val) gcsr_write(val, LOONGARCH_CSR_CPUID)
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#define read_gcsr_prcfg1() gcsr_read(LOONGARCH_CSR_PRCFG1)
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#define write_gcsr_prcfg1(val) gcsr_write(val, LOONGARCH_CSR_PRCFG1)
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#define read_gcsr_prcfg2() gcsr_read(LOONGARCH_CSR_PRCFG2)
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#define write_gcsr_prcfg2(val) gcsr_write(val, LOONGARCH_CSR_PRCFG2)
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#define read_gcsr_prcfg3() gcsr_read(LOONGARCH_CSR_PRCFG3)
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#define write_gcsr_prcfg3(val) gcsr_write(val, LOONGARCH_CSR_PRCFG3)
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#define read_gcsr_kscratch0() gcsr_read(LOONGARCH_CSR_KS0)
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#define write_gcsr_kscratch0(val) gcsr_write(val, LOONGARCH_CSR_KS0)
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#define read_gcsr_kscratch1() gcsr_read(LOONGARCH_CSR_KS1)
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#define write_gcsr_kscratch1(val) gcsr_write(val, LOONGARCH_CSR_KS1)
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#define read_gcsr_kscratch2() gcsr_read(LOONGARCH_CSR_KS2)
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#define write_gcsr_kscratch2(val) gcsr_write(val, LOONGARCH_CSR_KS2)
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#define read_gcsr_kscratch3() gcsr_read(LOONGARCH_CSR_KS3)
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#define write_gcsr_kscratch3(val) gcsr_write(val, LOONGARCH_CSR_KS3)
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#define read_gcsr_kscratch4() gcsr_read(LOONGARCH_CSR_KS4)
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#define write_gcsr_kscratch4(val) gcsr_write(val, LOONGARCH_CSR_KS4)
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#define read_gcsr_kscratch5() gcsr_read(LOONGARCH_CSR_KS5)
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#define write_gcsr_kscratch5(val) gcsr_write(val, LOONGARCH_CSR_KS5)
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#define read_gcsr_kscratch6() gcsr_read(LOONGARCH_CSR_KS6)
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#define write_gcsr_kscratch6(val) gcsr_write(val, LOONGARCH_CSR_KS6)
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#define read_gcsr_kscratch7() gcsr_read(LOONGARCH_CSR_KS7)
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#define write_gcsr_kscratch7(val) gcsr_write(val, LOONGARCH_CSR_KS7)
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#define read_gcsr_timerid() gcsr_read(LOONGARCH_CSR_TMID)
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#define write_gcsr_timerid(val) gcsr_write(val, LOONGARCH_CSR_TMID)
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#define read_gcsr_timercfg() gcsr_read(LOONGARCH_CSR_TCFG)
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#define write_gcsr_timercfg(val) gcsr_write(val, LOONGARCH_CSR_TCFG)
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#define read_gcsr_timertick() gcsr_read(LOONGARCH_CSR_TVAL)
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#define write_gcsr_timertick(val) gcsr_write(val, LOONGARCH_CSR_TVAL)
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#define read_gcsr_timeroffset() gcsr_read(LOONGARCH_CSR_CNTC)
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#define write_gcsr_timeroffset(val) gcsr_write(val, LOONGARCH_CSR_CNTC)
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#define read_gcsr_llbctl() gcsr_read(LOONGARCH_CSR_LLBCTL)
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#define write_gcsr_llbctl(val) gcsr_write(val, LOONGARCH_CSR_LLBCTL)
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#define read_gcsr_tlbidx() gcsr_read(LOONGARCH_CSR_TLBIDX)
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#define write_gcsr_tlbidx(val) gcsr_write(val, LOONGARCH_CSR_TLBIDX)
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#define read_gcsr_tlbrentry() gcsr_read(LOONGARCH_CSR_TLBRENTRY)
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#define write_gcsr_tlbrentry(val) gcsr_write(val, LOONGARCH_CSR_TLBRENTRY)
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#define read_gcsr_tlbrbadv() gcsr_read(LOONGARCH_CSR_TLBRBADV)
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#define write_gcsr_tlbrbadv(val) gcsr_write(val, LOONGARCH_CSR_TLBRBADV)
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#define read_gcsr_tlbrera() gcsr_read(LOONGARCH_CSR_TLBRERA)
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#define write_gcsr_tlbrera(val) gcsr_write(val, LOONGARCH_CSR_TLBRERA)
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#define read_gcsr_tlbrsave() gcsr_read(LOONGARCH_CSR_TLBRSAVE)
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#define write_gcsr_tlbrsave(val) gcsr_write(val, LOONGARCH_CSR_TLBRSAVE)
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#define read_gcsr_tlbrelo0() gcsr_read(LOONGARCH_CSR_TLBRELO0)
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#define write_gcsr_tlbrelo0(val) gcsr_write(val, LOONGARCH_CSR_TLBRELO0)
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#define read_gcsr_tlbrelo1() gcsr_read(LOONGARCH_CSR_TLBRELO1)
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#define write_gcsr_tlbrelo1(val) gcsr_write(val, LOONGARCH_CSR_TLBRELO1)
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#define read_gcsr_tlbrehi() gcsr_read(LOONGARCH_CSR_TLBREHI)
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#define write_gcsr_tlbrehi(val) gcsr_write(val, LOONGARCH_CSR_TLBREHI)
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#define read_gcsr_tlbrprmd() gcsr_read(LOONGARCH_CSR_TLBRPRMD)
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#define write_gcsr_tlbrprmd(val) gcsr_write(val, LOONGARCH_CSR_TLBRPRMD)
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#define read_gcsr_directwin0() gcsr_read(LOONGARCH_CSR_DMWIN0)
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#define write_gcsr_directwin0(val) gcsr_write(val, LOONGARCH_CSR_DMWIN0)
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#define read_gcsr_directwin1() gcsr_read(LOONGARCH_CSR_DMWIN1)
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#define write_gcsr_directwin1(val) gcsr_write(val, LOONGARCH_CSR_DMWIN1)
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#define read_gcsr_directwin2() gcsr_read(LOONGARCH_CSR_DMWIN2)
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#define write_gcsr_directwin2(val) gcsr_write(val, LOONGARCH_CSR_DMWIN2)
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#define read_gcsr_directwin3() gcsr_read(LOONGARCH_CSR_DMWIN3)
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#define write_gcsr_directwin3(val) gcsr_write(val, LOONGARCH_CSR_DMWIN3)
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/* Guest related CSRs */
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#define read_csr_gtlbc() csr_read64(LOONGARCH_CSR_GTLBC)
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#define write_csr_gtlbc(val) csr_write64(val, LOONGARCH_CSR_GTLBC)
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#define read_csr_trgp() csr_read64(LOONGARCH_CSR_TRGP)
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#define read_csr_gcfg() csr_read64(LOONGARCH_CSR_GCFG)
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#define write_csr_gcfg(val) csr_write64(val, LOONGARCH_CSR_GCFG)
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#define read_csr_gstat() csr_read64(LOONGARCH_CSR_GSTAT)
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#define write_csr_gstat(val) csr_write64(val, LOONGARCH_CSR_GSTAT)
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#define read_csr_gintc() csr_read64(LOONGARCH_CSR_GINTC)
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#define write_csr_gintc(val) csr_write64(val, LOONGARCH_CSR_GINTC)
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#define read_csr_gcntc() csr_read64(LOONGARCH_CSR_GCNTC)
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#define write_csr_gcntc(val) csr_write64(val, LOONGARCH_CSR_GCNTC)
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#define __BUILD_GCSR_OP(name) __BUILD_CSR_COMMON(gcsr_##name)
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__BUILD_CSR_OP(gcfg)
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__BUILD_CSR_OP(gstat)
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__BUILD_CSR_OP(gtlbc)
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__BUILD_CSR_OP(gintc)
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__BUILD_GCSR_OP(llbctl)
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__BUILD_GCSR_OP(tlbidx)
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#define set_gcsr_estat(val) \
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gcsr_xchg(val, val, LOONGARCH_CSR_ESTAT)
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#define clear_gcsr_estat(val) \
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gcsr_xchg(~(val), val, LOONGARCH_CSR_ESTAT)
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#define kvm_read_hw_gcsr(id) gcsr_read(id)
179+
#define kvm_write_hw_gcsr(id, val) gcsr_write(val, id)
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#define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid))
182+
#define kvm_restore_hw_gcsr(csr, gid) (gcsr_write(csr->csrs[gid], gid))
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int kvm_emu_iocsr(larch_inst inst, struct kvm_run *run, struct kvm_vcpu *vcpu);
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static __always_inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid)
187+
{
188+
return csr->csrs[gid];
189+
}
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static __always_inline void kvm_write_sw_gcsr(struct loongarch_csrs *csr, int gid, unsigned long val)
192+
{
193+
csr->csrs[gid] = val;
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}
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static __always_inline void kvm_set_sw_gcsr(struct loongarch_csrs *csr,
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int gid, unsigned long val)
198+
{
199+
csr->csrs[gid] |= val;
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}
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static __always_inline void kvm_change_sw_gcsr(struct loongarch_csrs *csr,
203+
int gid, unsigned long mask, unsigned long val)
204+
{
205+
unsigned long _mask = mask;
206+
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csr->csrs[gid] &= ~_mask;
208+
csr->csrs[gid] |= val & _mask;
209+
}
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#endif /* __ASM_LOONGARCH_KVM_CSR_H__ */

‎arch/loongarch/include/asm/kvm_vcpu.h

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@@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_LOONGARCH_KVM_VCPU_H__
7+
#define __ASM_LOONGARCH_KVM_VCPU_H__
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#include <linux/kvm_host.h>
10+
#include <asm/loongarch.h>
11+
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/* Controlled by 0x5 guest estat */
13+
#define CPU_SIP0 (_ULCAST_(1))
14+
#define CPU_SIP1 (_ULCAST_(1) << 1)
15+
#define CPU_PMU (_ULCAST_(1) << 10)
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#define CPU_TIMER (_ULCAST_(1) << 11)
17+
#define CPU_IPI (_ULCAST_(1) << 12)
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/* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */
20+
#define CPU_IP0 (_ULCAST_(1))
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#define CPU_IP1 (_ULCAST_(1) << 1)
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#define CPU_IP2 (_ULCAST_(1) << 2)
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#define CPU_IP3 (_ULCAST_(1) << 3)
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#define CPU_IP4 (_ULCAST_(1) << 4)
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#define CPU_IP5 (_ULCAST_(1) << 5)
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#define CPU_IP6 (_ULCAST_(1) << 6)
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#define CPU_IP7 (_ULCAST_(1) << 7)
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#define MNSEC_PER_SEC (NSEC_PER_SEC >> 20)
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_LOONGSON_IRQ_TYPE_SHIFT 24
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#define KVM_LOONGSON_IRQ_TYPE_MASK 0xff
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#define KVM_LOONGSON_IRQ_VCPU_SHIFT 16
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#define KVM_LOONGSON_IRQ_VCPU_MASK 0xff
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#define KVM_LOONGSON_IRQ_NUM_SHIFT 0
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#define KVM_LOONGSON_IRQ_NUM_MASK 0xffff
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typedef union loongarch_instruction larch_inst;
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typedef int (*exit_handle_fn)(struct kvm_vcpu *);
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int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst);
43+
int kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst);
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int kvm_complete_mmio_read(struct kvm_vcpu *vcpu, struct kvm_run *run);
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int kvm_complete_iocsr_read(struct kvm_vcpu *vcpu, struct kvm_run *run);
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int kvm_emu_idle(struct kvm_vcpu *vcpu);
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int kvm_pending_timer(struct kvm_vcpu *vcpu);
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int kvm_handle_fault(struct kvm_vcpu *vcpu, int fault);
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void kvm_deliver_intr(struct kvm_vcpu *vcpu);
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void kvm_deliver_exception(struct kvm_vcpu *vcpu);
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void kvm_own_fpu(struct kvm_vcpu *vcpu);
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void kvm_lose_fpu(struct kvm_vcpu *vcpu);
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void kvm_save_fpu(struct loongarch_fpu *fpu);
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void kvm_restore_fpu(struct loongarch_fpu *fpu);
56+
void kvm_restore_fcsr(struct loongarch_fpu *fpu);
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58+
void kvm_acquire_timer(struct kvm_vcpu *vcpu);
59+
void kvm_init_timer(struct kvm_vcpu *vcpu, unsigned long hz);
60+
void kvm_reset_timer(struct kvm_vcpu *vcpu);
61+
void kvm_save_timer(struct kvm_vcpu *vcpu);
62+
void kvm_restore_timer(struct kvm_vcpu *vcpu);
63+
64+
int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq);
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/*
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* Loongarch KVM guest interrupt handling
68+
*/
69+
static inline void kvm_queue_irq(struct kvm_vcpu *vcpu, unsigned int irq)
70+
{
71+
set_bit(irq, &vcpu->arch.irq_pending);
72+
clear_bit(irq, &vcpu->arch.irq_clear);
73+
}
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static inline void kvm_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int irq)
76+
{
77+
clear_bit(irq, &vcpu->arch.irq_pending);
78+
set_bit(irq, &vcpu->arch.irq_clear);
79+
}
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81+
static inline int kvm_queue_exception(struct kvm_vcpu *vcpu,
82+
unsigned int code, unsigned int subcode)
83+
{
84+
/* only one exception can be injected */
85+
if (!vcpu->arch.exception_pending) {
86+
set_bit(code, &vcpu->arch.exception_pending);
87+
vcpu->arch.esubcode = subcode;
88+
return 0;
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} else
90+
return -1;
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}
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#endif /* __ASM_LOONGARCH_KVM_VCPU_H__ */

‎arch/loongarch/include/asm/loongarch.h

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -226,6 +226,7 @@
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#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
227227
#define CSR_ECFG_VS_SHIFT 16
228228
#define CSR_ECFG_VS_WIDTH 3
229+
#define CSR_ECFG_VS_SHIFT_END (CSR_ECFG_VS_SHIFT + CSR_ECFG_VS_WIDTH - 1)
229230
#define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
230231
#define CSR_ECFG_IM_SHIFT 0
231232
#define CSR_ECFG_IM_WIDTH 14
@@ -314,13 +315,14 @@
314315
#define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
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316317
#define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */
317-
#define CSR_GTLBC_RID_SHIFT 16
318-
#define CSR_GTLBC_RID_WIDTH 8
319-
#define CSR_GTLBC_RID (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT)
318+
#define CSR_GTLBC_TGID_SHIFT 16
319+
#define CSR_GTLBC_TGID_WIDTH 8
320+
#define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
321+
#define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
320322
#define CSR_GTLBC_TOTI_SHIFT 13
321323
#define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
322-
#define CSR_GTLBC_USERID_SHIFT 12
323-
#define CSR_GTLBC_USERID (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT)
324+
#define CSR_GTLBC_USETGID_SHIFT 12
325+
#define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT)
324326
#define CSR_GTLBC_GMTLBSZ_SHIFT 0
325327
#define CSR_GTLBC_GMTLBSZ_WIDTH 6
326328
#define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
@@ -475,6 +477,7 @@
475477
#define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */
476478
#define CSR_GSTAT_GID_SHIFT 16
477479
#define CSR_GSTAT_GID_WIDTH 8
480+
#define CSR_GSTAT_GID_SHIFT_END (CSR_GSTAT_GID_SHIFT + CSR_GSTAT_GID_WIDTH - 1)
478481
#define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
479482
#define CSR_GSTAT_GIDBIT_SHIFT 4
480483
#define CSR_GSTAT_GIDBIT_WIDTH 6
@@ -525,6 +528,12 @@
525528
#define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
526529
#define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
527530
#define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
531+
#define CSR_GCFG_MATP_NEST_SHIFT 2
532+
#define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT)
533+
#define CSR_GCFG_MATP_ROOT_SHIFT 1
534+
#define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT)
535+
#define CSR_GCFG_MATP_GUEST_SHIFT 0
536+
#define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT)
528537

529538
#define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */
530539
#define CSR_GINTC_HC_SHIFT 16

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