@@ -1775,8 +1775,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
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return ;
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pci_read_config_dword (pdev , pos + PCI_REBAR_CTRL , & ctrl );
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- nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK ) >>
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- PCI_REBAR_CTRL_NBAR_SHIFT ;
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+ nbars = FIELD_GET (PCI_REBAR_CTRL_NBAR_MASK , ctrl );
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for (i = 0 ; i < nbars ; i ++ , pos += 8 ) {
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struct resource * res ;
@@ -1787,7 +1786,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
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res = pdev -> resource + bar_idx ;
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size = pci_rebar_bytes_to_size (resource_size (res ));
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ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE ;
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- ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT ;
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+ ctrl |= FIELD_PREP ( PCI_REBAR_CTRL_BAR_SIZE , size ) ;
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pci_write_config_dword (pdev , pos + PCI_REBAR_CTRL , ctrl );
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}
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}
@@ -3228,7 +3227,7 @@ void pci_pm_init(struct pci_dev *dev)
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(pmc & PCI_PM_CAP_PME_D2 ) ? " D2" : "" ,
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(pmc & PCI_PM_CAP_PME_D3hot ) ? " D3hot" : "" ,
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(pmc & PCI_PM_CAP_PME_D3cold ) ? " D3cold" : "" );
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- dev -> pme_support = pmc >> PCI_PM_CAP_PME_SHIFT ;
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+ dev -> pme_support = FIELD_GET ( PCI_PM_CAP_PME_MASK , pmc ) ;
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dev -> pme_poll = true;
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/*
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* Make device's PM flags reflect the wake-up capability, but
@@ -3299,20 +3298,20 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
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ent_offset += 4 ;
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/* Entry size field indicates DWORDs after 1st */
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- ent_size = (( dw0 & PCI_EA_ES ) + 1 ) << 2 ;
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+ ent_size = (FIELD_GET ( PCI_EA_ES , dw0 ) + 1 ) << 2 ;
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if (!(dw0 & PCI_EA_ENABLE )) /* Entry not enabled */
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goto out ;
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- bei = ( dw0 & PCI_EA_BEI ) >> 4 ;
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- prop = ( dw0 & PCI_EA_PP ) >> 8 ;
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+ bei = FIELD_GET ( PCI_EA_BEI , dw0 ) ;
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+ prop = FIELD_GET ( PCI_EA_PP , dw0 ) ;
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/*
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* If the Property is in the reserved range, try the Secondary
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* Property instead.
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*/
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if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED )
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- prop = ( dw0 & PCI_EA_SP ) >> 16 ;
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+ prop = FIELD_GET ( PCI_EA_SP , dw0 ) ;
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if (prop > PCI_EA_P_BRIDGE_IO )
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goto out ;
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@@ -3719,14 +3718,13 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
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return - ENOTSUPP ;
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pci_read_config_dword (pdev , pos + PCI_REBAR_CTRL , & ctrl );
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- nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK ) >>
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- PCI_REBAR_CTRL_NBAR_SHIFT ;
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+ nbars = FIELD_GET (PCI_REBAR_CTRL_NBAR_MASK , ctrl );
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for (i = 0 ; i < nbars ; i ++ , pos += 8 ) {
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int bar_idx ;
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pci_read_config_dword (pdev , pos + PCI_REBAR_CTRL , & ctrl );
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- bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX ;
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+ bar_idx = FIELD_GET ( PCI_REBAR_CTRL_BAR_IDX , ctrl ) ;
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if (bar_idx == bar )
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return pos ;
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}
@@ -3781,7 +3779,7 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
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return pos ;
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pci_read_config_dword (pdev , pos + PCI_REBAR_CTRL , & ctrl );
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- return ( ctrl & PCI_REBAR_CTRL_BAR_SIZE ) >> PCI_REBAR_CTRL_BAR_SHIFT ;
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+ return FIELD_GET ( PCI_REBAR_CTRL_BAR_SIZE , ctrl ) ;
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}
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/**
@@ -3804,7 +3802,7 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
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pci_read_config_dword (pdev , pos + PCI_REBAR_CTRL , & ctrl );
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ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE ;
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- ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT ;
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+ ctrl |= FIELD_PREP ( PCI_REBAR_CTRL_BAR_SIZE , size ) ;
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pci_write_config_dword (pdev , pos + PCI_REBAR_CTRL , ctrl );
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return 0 ;
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}
@@ -6042,7 +6040,7 @@ int pcix_get_max_mmrbc(struct pci_dev *dev)
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if (pci_read_config_dword (dev , cap + PCI_X_STATUS , & stat ))
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return - EINVAL ;
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- return 512 << (( stat & PCI_X_STATUS_MAX_READ ) >> 21 );
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+ return 512 << FIELD_GET ( PCI_X_STATUS_MAX_READ , stat );
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}
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EXPORT_SYMBOL (pcix_get_max_mmrbc );
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@@ -6065,7 +6063,7 @@ int pcix_get_mmrbc(struct pci_dev *dev)
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if (pci_read_config_word (dev , cap + PCI_X_CMD , & cmd ))
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return - EINVAL ;
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- return 512 << (( cmd & PCI_X_CMD_MAX_READ ) >> 2 );
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+ return 512 << FIELD_GET ( PCI_X_CMD_MAX_READ , cmd );
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}
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EXPORT_SYMBOL (pcix_get_mmrbc );
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@@ -6096,19 +6094,19 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
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if (pci_read_config_dword (dev , cap + PCI_X_STATUS , & stat ))
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return - EINVAL ;
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- if (v > ( stat & PCI_X_STATUS_MAX_READ ) >> 21 )
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+ if (v > FIELD_GET ( PCI_X_STATUS_MAX_READ , stat ) )
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return - E2BIG ;
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if (pci_read_config_word (dev , cap + PCI_X_CMD , & cmd ))
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return - EINVAL ;
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- o = ( cmd & PCI_X_CMD_MAX_READ ) >> 2 ;
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+ o = FIELD_GET ( PCI_X_CMD_MAX_READ , cmd ) ;
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if (o != v ) {
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if (v > o && (dev -> bus -> bus_flags & PCI_BUS_FLAGS_NO_MMRBC ))
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return - EIO ;
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cmd &= ~PCI_X_CMD_MAX_READ ;
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- cmd |= v << 2 ;
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+ cmd |= FIELD_PREP ( PCI_X_CMD_MAX_READ , v ) ;
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if (pci_write_config_word (dev , cap + PCI_X_CMD , cmd ))
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return - EIO ;
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}
@@ -6128,7 +6126,7 @@ int pcie_get_readrq(struct pci_dev *dev)
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pcie_capability_read_word (dev , PCI_EXP_DEVCTL , & ctl );
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- return 128 << (( ctl & PCI_EXP_DEVCTL_READRQ ) >> 12 );
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+ return 128 << FIELD_GET ( PCI_EXP_DEVCTL_READRQ , ctl );
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}
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EXPORT_SYMBOL (pcie_get_readrq );
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@@ -6161,7 +6159,7 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
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rq = mps ;
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}
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- v = ( ffs (rq ) - 8 ) << 12 ;
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+ v = FIELD_PREP ( PCI_EXP_DEVCTL_READRQ , ffs (rq ) - 8 );
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if (bridge -> no_inc_mrrs ) {
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int max_mrrs = pcie_get_readrq (dev );
@@ -6191,7 +6189,7 @@ int pcie_get_mps(struct pci_dev *dev)
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pcie_capability_read_word (dev , PCI_EXP_DEVCTL , & ctl );
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- return 128 << (( ctl & PCI_EXP_DEVCTL_PAYLOAD ) >> 5 );
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+ return 128 << FIELD_GET ( PCI_EXP_DEVCTL_PAYLOAD , ctl );
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}
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EXPORT_SYMBOL (pcie_get_mps );
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@@ -6214,7 +6212,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
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v = ffs (mps ) - 8 ;
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if (v > dev -> pcie_mpss )
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return - EINVAL ;
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- v <<= 5 ;
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+ v = FIELD_PREP ( PCI_EXP_DEVCTL_PAYLOAD , v ) ;
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ret = pcie_capability_clear_and_set_word (dev , PCI_EXP_DEVCTL ,
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PCI_EXP_DEVCTL_PAYLOAD , v );
@@ -6256,7 +6254,8 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
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while (dev ) {
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pcie_capability_read_word (dev , PCI_EXP_LNKSTA , & lnksta );
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- next_speed = pcie_link_speed [lnksta & PCI_EXP_LNKSTA_CLS ];
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+ next_speed = pcie_link_speed [FIELD_GET (PCI_EXP_LNKSTA_CLS ,
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+ lnksta )];
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next_width = FIELD_GET (PCI_EXP_LNKSTA_NLW , lnksta );
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next_bw = next_width * PCIE_SPEED2MBS_ENC (next_speed );
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