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179 | 179 |
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180 | 180 | struct rspi_data {
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181 | 181 | void __iomem *addr;
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182 |
| - u32 max_speed_hz; |
| 182 | + u32 speed_hz; |
183 | 183 | struct spi_controller *ctlr;
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184 | 184 | struct platform_device *pdev;
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185 | 185 | wait_queue_head_t wait;
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@@ -258,8 +258,7 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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258 | 258 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
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259 | 259 |
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260 | 260 | /* Sets transfer bit rate */
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261 |
| - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), |
262 |
| - 2 * rspi->max_speed_hz) - 1; |
| 261 | + spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz) - 1; |
263 | 262 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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264 | 263 |
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265 | 264 | /* Disable dummy transmission, set 16-bit word access, 1 frame */
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@@ -299,14 +298,14 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
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299 | 298 |
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300 | 299 | clksrc = clk_get_rate(rspi->clk);
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301 | 300 | while (div < 3) {
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302 |
| - if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ |
| 301 | + if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */ |
303 | 302 | break;
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304 | 303 | div++;
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305 | 304 | clksrc /= 2;
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306 | 305 | }
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307 | 306 |
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308 | 307 | /* Sets transfer bit rate */
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309 |
| - spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1; |
| 308 | + spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1; |
310 | 309 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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311 | 310 | rspi->spcmd |= div << 2;
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312 | 311 |
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@@ -341,7 +340,7 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
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341 | 340 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
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342 | 341 |
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343 | 342 | /* Sets transfer bit rate */
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344 |
| - spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); |
| 343 | + spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->speed_hz); |
345 | 344 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
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346 | 345 |
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347 | 346 | /* Disable dummy transmission, set byte access */
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@@ -949,9 +948,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
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949 | 948 | {
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950 | 949 | struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
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951 | 950 | struct spi_device *spi = msg->spi;
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| 951 | + const struct spi_transfer *xfer; |
952 | 952 | int ret;
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953 | 953 |
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954 |
| - rspi->max_speed_hz = spi->max_speed_hz; |
| 954 | + /* |
| 955 | + * As the Bit Rate Register must not be changed while the device is |
| 956 | + * active, all transfers in a message must use the same bit rate. |
| 957 | + * In theory, the sequencer could be enabled, and each Command Register |
| 958 | + * could divide the base bit rate by a different value. |
| 959 | + * However, most RSPI variants do not have Transfer Data Length |
| 960 | + * Multiplier Setting Registers, so each sequence step would be limited |
| 961 | + * to a single word, making this feature unsuitable for large |
| 962 | + * transfers, which would gain most from it. |
| 963 | + */ |
| 964 | + rspi->speed_hz = spi->max_speed_hz; |
| 965 | + list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 966 | + if (xfer->speed_hz < rspi->speed_hz) |
| 967 | + rspi->speed_hz = xfer->speed_hz; |
| 968 | + } |
955 | 969 |
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956 | 970 | rspi->spcmd = SPCMD_SSLKP;
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957 | 971 | if (spi->mode & SPI_CPOL)
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