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pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will be used by gpio-rockchip driver in the future. Signed-off-by: Jianqun Xu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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drivers/pinctrl/pinctrl-rockchip.c

Lines changed: 1 addition & 225 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737

3838
#include "core.h"
3939
#include "pinconf.h"
40+
#include "pinctrl-rockchip.h"
4041

4142
/* GPIO control registers */
4243
#define GPIO_SWPORT_DR 0x00
@@ -52,21 +53,6 @@
5253
#define GPIO_EXT_PORT 0x50
5354
#define GPIO_LS_SYNC 0x60
5455

55-
enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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RK2928,
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RK3066B,
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RK3128,
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RK3188,
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RK3288,
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RK3308,
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RK3368,
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RK3399,
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RK3568,
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};
68-
69-
7056
/**
7157
* Generate a bitmask for setting a value (v) with a write mask bit in hiword
7258
* register 31:16 area.
@@ -84,103 +70,6 @@ enum rockchip_pinctrl_type {
8470
#define IOMUX_WIDTH_3BIT BIT(4)
8571
#define IOMUX_WIDTH_2BIT BIT(5)
8672

87-
/**
88-
* struct rockchip_iomux
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* @type: iomux variant using IOMUX_* constants
90-
* @offset: if initialized to -1 it will be autocalculated, by specifying
91-
* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
93-
*/
94-
struct rockchip_iomux {
95-
int type;
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int offset;
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};
98-
99-
/*
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
102-
enum rockchip_pin_drv_type {
103-
DRV_TYPE_IO_DEFAULT = 0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_MAX
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};
110-
111-
/*
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
114-
enum rockchip_pin_pull_type {
115-
PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
119-
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/**
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* struct rockchip_drv
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
124-
* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following drive strength
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* registers. if used chips own cal_drv func instead to calculate
127-
* registers offset, the variant could be ignored.
128-
*/
129-
struct rockchip_drv {
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enum rockchip_pin_drv_type drv_type;
131-
int offset;
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};
133-
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/**
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* struct rockchip_pin_bank
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* @reg_base: register base of the gpio bank
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* @regmap_pull: optional separate register for additional pull settings
138-
* @clk: clock of the gpio bank
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* @irq: interrupt of the gpio bank
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* @saved_masks: Saved content of GPIO_INTEN at suspend time.
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @valid: is all necessary information present
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* @of_node: dt node of this bank
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* @drvdata: common pinctrl basedata
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* @domain: irqdomain of the gpio bank
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* @gpio_chip: gpiolib chip
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* @grange: gpio range
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* @slock: spinlock for the gpio bank
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* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
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* @recalced_mask: bit mask to indicate a need to recalulate the mask
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* @route_mask: bits describing the routing pins of per bank
158-
*/
159-
struct rockchip_pin_bank {
160-
void __iomem *reg_base;
161-
struct regmap *regmap_pull;
162-
struct clk *clk;
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int irq;
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u32 saved_masks;
165-
u32 pin_base;
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u8 nr_pins;
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char *name;
168-
u8 bank_num;
169-
struct rockchip_iomux iomux[4];
170-
struct rockchip_drv drv[4];
171-
enum rockchip_pin_pull_type pull_type[4];
172-
bool valid;
173-
struct device_node *of_node;
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struct rockchip_pinctrl *drvdata;
175-
struct irq_domain *domain;
176-
struct gpio_chip gpio_chip;
177-
struct pinctrl_gpio_range grange;
178-
raw_spinlock_t slock;
179-
u32 toggle_edge_mode;
180-
u32 recalced_mask;
181-
u32 route_mask;
182-
};
183-
18473
#define PIN_BANK(id, pins, label) \
18574
{ \
18675
.bank_num = id, \
@@ -320,119 +209,6 @@ struct rockchip_pin_bank {
320209
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
321210
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
322211

323-
/**
324-
* struct rockchip_mux_recalced_data: represent a pin iomux data.
325-
* @num: bank number.
326-
* @pin: pin number.
327-
* @bit: index at register.
328-
* @reg: register offset.
329-
* @mask: mask bit
330-
*/
331-
struct rockchip_mux_recalced_data {
332-
u8 num;
333-
u8 pin;
334-
u32 reg;
335-
u8 bit;
336-
u8 mask;
337-
};
338-
339-
enum rockchip_mux_route_location {
340-
ROCKCHIP_ROUTE_SAME = 0,
341-
ROCKCHIP_ROUTE_PMU,
342-
ROCKCHIP_ROUTE_GRF,
343-
};
344-
345-
/**
346-
* struct rockchip_mux_recalced_data: represent a pin iomux data.
347-
* @bank_num: bank number.
348-
* @pin: index at register or used to calc index.
349-
* @func: the min pin.
350-
* @route_location: the mux route location (same, pmu, grf).
351-
* @route_offset: the max pin.
352-
* @route_val: the register offset.
353-
*/
354-
struct rockchip_mux_route_data {
355-
u8 bank_num;
356-
u8 pin;
357-
u8 func;
358-
enum rockchip_mux_route_location route_location;
359-
u32 route_offset;
360-
u32 route_val;
361-
};
362-
363-
struct rockchip_pin_ctrl {
364-
struct rockchip_pin_bank *pin_banks;
365-
u32 nr_banks;
366-
u32 nr_pins;
367-
char *label;
368-
enum rockchip_pinctrl_type type;
369-
int grf_mux_offset;
370-
int pmu_mux_offset;
371-
int grf_drv_offset;
372-
int pmu_drv_offset;
373-
struct rockchip_mux_recalced_data *iomux_recalced;
374-
u32 niomux_recalced;
375-
struct rockchip_mux_route_data *iomux_routes;
376-
u32 niomux_routes;
377-
378-
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
379-
int pin_num, struct regmap **regmap,
380-
int *reg, u8 *bit);
381-
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
382-
int pin_num, struct regmap **regmap,
383-
int *reg, u8 *bit);
384-
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
385-
int pin_num, struct regmap **regmap,
386-
int *reg, u8 *bit);
387-
};
388-
389-
struct rockchip_pin_config {
390-
unsigned int func;
391-
unsigned long *configs;
392-
unsigned int nconfigs;
393-
};
394-
395-
/**
396-
* struct rockchip_pin_group: represent group of pins of a pinmux function.
397-
* @name: name of the pin group, used to lookup the group.
398-
* @pins: the pins included in this group.
399-
* @npins: number of pins included in this group.
400-
* @data: local pin configuration
401-
*/
402-
struct rockchip_pin_group {
403-
const char *name;
404-
unsigned int npins;
405-
unsigned int *pins;
406-
struct rockchip_pin_config *data;
407-
};
408-
409-
/**
410-
* struct rockchip_pmx_func: represent a pin function.
411-
* @name: name of the pin function, used to lookup the function.
412-
* @groups: one or more names of pin groups that provide this function.
413-
* @ngroups: number of groups included in @groups.
414-
*/
415-
struct rockchip_pmx_func {
416-
const char *name;
417-
const char **groups;
418-
u8 ngroups;
419-
};
420-
421-
struct rockchip_pinctrl {
422-
struct regmap *regmap_base;
423-
int reg_size;
424-
struct regmap *regmap_pull;
425-
struct regmap *regmap_pmu;
426-
struct device *dev;
427-
struct rockchip_pin_ctrl *ctrl;
428-
struct pinctrl_desc pctl;
429-
struct pinctrl_dev *pctl_dev;
430-
struct rockchip_pin_group *groups;
431-
unsigned int ngroups;
432-
struct rockchip_pmx_func *functions;
433-
unsigned int nfunctions;
434-
};
435-
436212
static struct regmap_config rockchip_regmap_config = {
437213
.reg_bits = 32,
438214
.val_bits = 32,

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